Double-barrier Magnetic Tunnel Junctions Research Articles

Tunnel-magneto resistance of double-barrier tunnel junctions in the presence of spin-orbit coupling within spin-filter barriers

The tunnel magneto-resistance ratio is investigated for double-barrier tunnel junctions with spin-filter (magnetic insulators) barriers. The transmission probability is calculated in the tight-binding model by the non-equilibrium Green's function formalism considering spin-orbit coupling within barriers. The formation of resonant states inside a non-magnetic spacer gives rise to an enhancement in tunnel magneto-resistance ratio. Double spin-filter tunnel junctions have also shown a higher tunnel magneto-resistance ratio compared to that in double-barrier magnetic tunnel junctions. These findings will be valuable to improve the performance of spintronics devices.

XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (–50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing

This brief deals with the impact of spin-transfer torque magnetic random access memory (STT-MRAM) cell based on double-barrier magnetic tunnel junction (DMTJ) on the performance of a two-layer multilayer perceptron (MLP) neural network. The DMTJ-based cell is benchmarked against the conventional single-barrier MTJ (SMTJ) counterpart by means of a comprehensive evaluation carried out through a state-of-the-art device-to-algorithm simulation framework. The benchmark is based on the MNIST handwritten dataset, Verilog-A MTJ compact models developed by our group, and 0.8 V FinFET technology. Our results point out that the use of DMTJ-based STT-MRAM cells to implement digital embedded non-volatile memory (eNVM) synaptic core allows write/read energy and latency improvements of about 53%/61% and 66%/17%, respectively, as compared to the SMTJ-based equivalent design. This is achieved by ensuring a reduced area footprint and a learning accuracy of about 91%. Such results make the DMTJ-based STT-MRAM cell a good eNVM option for neuro-inspired computing.

Giant tunneling magnetoresistance in in-plane double-barrier magnetic tunnel junctions based on MXene Cr2C.

The discovery of two-dimensional (2D) magnetic materials makes it possible to realize in-plane magnetic tunnel junctions. In this study, the transport characteristics of an in-plane double barrier magnetic tunnel junction (IDB-MTJ) based on Cr2C have been studied by density functional theory combined with the nonequilibrium Green's function method. The results showed its maximum tunneling magnetoresistance ratio (TMR) value reached 6.58 × 1010. Its minimum TMR value (3.86 × 106) was also comparable to those of conventional field effect transistors (FETs). Due to its giant TMR and unique structural characteristics, the IDB-MTJ based on Cr2C has great potential applications in magnetic random access memory (MRAM) and logic computing.

Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs

This paper investigates the impact of thermal stability relaxation in double-barrier magnetic tunnel junctions (DMTJs) for energy-efficient spin-transfer torque magnetic random access memories (STT-MRAMs) operating at the liquid nitrogen boiling point (77 K). Our study is carried out through a macrospin-based Verilog-A compact model of DMTJ, along with a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. Comprehensive bitcell-level electrical characterization is used to estimate the energy/latency per operation and leakage power at the memory architecture-level. As a main result of our analysis, we show that energy-efficient small-to-large embedded memories can be obtained by significantly relaxing the non-volatility requirement of DMTJ devices at room temperature (i.e., by reducing the cross-section area), while maintaining the typical 10-years retention time at cryogenic temperatures. This makes DMTJ-based STT-MRAM operating at 77 K more energy-efficient than six-transistors static random-access memory (6T-SRAM) under both read and write accesses (−56% and −37% on average, respectively). Obtained results thus prove that DMTJ-based STT-MRAM with relaxed retention time is a promising alternative for the realization of reliable and energy-efficient embedded memories operating at cryogenic temperatures.

Tunable tunneling magnetoresistance in in-plane double barrier magnetic tunnel junctions based on B vacancy h-NB nanoribbons.

Magnetic tunnel junctions (MTJs) have attained new opportunities due to the emergence of two-dimensional (2D) magnetic materials after they were proposed more than forty years ago. Here, an in-plane double barrier magnetic tunnel junction (IDB-MTJ) based on B vacancy h-NB nanoribbons has been proposed firstly, and the transport properties have been studied using density functional theory combined with the nonequilibrium Green's function method. Due to its unique structural characteristics, the tunneling magnetoresistance (TMR) ratio can be tuned and the maximum TMR can reach 1.86 × 105. The potential applications of the IDB-MTJ in magnetic random-access memories and logical computation have also been discussed. We find that the IDB-MTJs have great potential in magnetic random-access memories and logical computation applications.

Embedded Memories for Cryogenic Applications

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

Unconventional bias dependence of tunnel magnetoresistance induced by the Coulomb blockade effect

In conventional magnetic tunnel junctions (MTJs), the tunnel magnetoresistance (TMR) monotonically decreases with increasing bias voltage, which limits the bias voltage range for the operation of MTJs. In our study, using double-barrier MTJs composed of Fe/MgO/Fe/γ-Al2O3 grown on a Nb-doped SrTiO3 substrate, we demonstrate unconventional bias dependences of the TMR, in which the TMR ratio increases with increasing bias voltage. We reveal that this behavior originates from the sharp giant resistance peak near zero bias likely induced by the Coulomb blockade effect via Fe impurities in γ-Al2O3, which are diffused from the Fe layer. The observed TMR ratio is 23% at a bias voltage of −4 V at 3.5 K, which is a very high value in this large bias voltage range. Our results offer a novel way to improve the bias voltage dependence of TMR.

Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET- and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (<0.5 V), while showing energy savings of 50% and faster write switching of 60%.

Relaxing non-volatility for energy-efficient DMTJ based cryogenic STT-MRAM

Spin-transfer torque magnetic random-access memory (STT-MRAM) is considered as a premiere candidate for replacing conventional six-transistors static random-access memory (6T-SRAM) in processor caches. This paper explores STT-MRAMs based on double-barrier magnetic tunnel junction with two reference layers (DMTJ), while operating at cryogenic temperatures (77 K). To deal with large dynamc energy and long latency of write operation, we suggest to significantly relax the non-volatility requirement of DMTJ devices at room temperature by reducing the cross-section area, while maintaining the typical 10-years retention time at the target operating temperature. This leads the cryogenic DMTJ-based STT-MRAM to be more energy-efficient than its 6T-SRAM counterpart under both read and write operations, while exhibiting smaller area footprint.

Spin Torque Efficiency Modulation in a Double-Barrier Magnetic Tunnel Junction with a Read/Write Mode Control Layer

Spin Torque Efficiency Modulation in a Double-Barrier Magnetic Tunnel Junction with a Read/Write Mode Control Layer

Simulation Analysis of DMTJ-Based STT-MRAM Operating at Cryogenic Temperatures

This article investigates spin-transfer torque magnetic random access memories (STT-MRAMs) based on double-barrier magnetic tunnel junction (DMTJ) with two reference layers when operating at cryogenic temperatures. Our study is based on architecture-level estimations relying on preliminary bitcell-level electrical simulations, which have been carried out by exploiting a macrospin-based Verilog-A compact model of DMTJ, along with a 65 nm cryogenic-aware CMOS technology. Compared to conventional six-transistor static random access memory (6T-SRAM), DMTJ-based STT-MRAM proves to be faster under read access and less energy-hungry under both read/write accesses for medium to large memory sizes. Quantitatively, compared to its 6T-SRAM counterpart, a 2 MB DMTJ-based STT-MRAM operating at 77 K improves read access time by 28% and energy consumption by 52% and 38% for read and write operations, respectively. This is achieved while providing considerably lower leakage power (-98%) and a smaller on-chip area (by about 3×), at the only cost of worsened write access time.

Spin-filtering effects of double-barrier magnetic tunnel junctions with an indium phosphide (InP) spacer

Spin-polarized currents in double-barrier magnetic tunnel junctions (MTJs) as CoFeB/MgO/InP/MgO/CoFeB (MTJs-InP) are investigated by non-equilibrium Green’s function formalism. The asymmetric structures with a half-metal LSMO contact are studied and a spin-diode behavior is found compared to the MTJs-InP. Charge and spin currents as well as spin polarization as a function of bias voltage, angle between magnetizations and quantum-well thickness are also described. A nearly 100% spin polarization is observed at a certain range of bias voltage. Therefore, one can design excellent spin-filter devices based on new MTJs-InP.

Large tunnel magnetoresistance in a fully epitaxial double-barrier magnetic tunnel junction of Fe/MgO/Fe/γ-Al2O3/Nb-doped SrTiO3

We report large tunnel magnetoresistance (TMR) ratios of up to 219% at 300 K and 366% at 3.7 K obtained for a high-quality fully epitaxial double-barrier magnetic tunnel junction (MTJ) composed of Fe/MgO/Fe/γ-Al2O3/Nb-doped SrTiO3. The obtained TMR ratios are among the highest values reported in Fe/MgO/Fe structures. This result may be attributed to the small in-plane wave vectors of the tunneling electrons injected from the Nb-doped SrTiO3 electrode with a small carrier density, demonstrating good compatibility between the Fe-based MTJ and SrTiO3.

Thermopower of double-barrier magnetic tunnel junctions with a middle La0.7Sr0.3MnO3 layer

Magnetic tunnel junctions (MTJs) are promising devices for heat-assisted magnetic recording technology. Quantum transport of nanoscale double-barrier MTJs with a middle La0.7Sr0.3MnO3 (LSMO) layer (DBMTJs-LSMO) is investigated by the non-equilibrium Green’s function formalism. The thermopower is described in the linear response regime. The results of the DBMTJs-LSMO show an enhancement of the thermopower compared to DBMTJs-CoFeB and conventional single-barrier MTJs (SBMTJs) due to the LSMO physical properties and also the existence of the quantum-well (QW) states. The parallel (P) and anti-parallel (AP) thermopower of and are achieved at room temperature for DBMTJs-LSMO. The tunnel magneto-thermopower ratio is found to be at room temperature along with its maximum value of at for DBMTJs-LSMO.

Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework

This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic random access memories (STT-MRAMs) based on state-of-the-art perpendicular magnetic tunnel junctions (MTJs) and FinFETs. The use of double-barrier MTJs with two reference layers (DMTJs) is benchmarked against solutions relying on single-barrier MTJs (SMTJs) at different technology nodes (from 28-nm down to 20-nm). Our study is carried out through a cross-layer simulation platform, starting from the device- up to the system-level. Our results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow decreasing write access time of about 63% as compared to their SMTJ-based counterparts. This is achieved while assuring reduced energy consumption under both write (−42%) and read (−28%) accesses, lower area occupancy (−40%) and smaller leakage power (−25%), at the only cost of worsened read access time. This makes DMTJ-based STT-MRAM a promising candidate to replace conventional semiconductor-based cache memory for the next-generation of low-power microprocessors with on-chip non-volatility.

Switching Performance Comparison With Low Switching Energy Due to Initial Temperature Increment in CoFeB/MgO-Based Single and Double Barriers

Spin-transfer torque magnetic random-access memory (STT-MRAM) based on a single-barrier magnetic tunnel junction (SBMTJ) and a double-barrier magnetic tunnel junction (DBMTJ) has evolved along with a low switching current and low energy consumption to obtain a high areal density and a fast switching speed. The increment of initial temperature, ${T}_{{\text {in}}}$ , in STT-MRAM can achieve low switching energy, ${E}_{{\text {SW}}}$ . However, this leads to an unavoidable decrease in $\Delta $ and switching efficiency. In this paper, SBMTJ and DBMTJ were analyzed in terms of the switching efficiency factor with ${E}_{{\text {SW}}}$ reduction by increasing the ${T}_{{\text {in}}}$ . The switching temperature, ${T}_{{\text {SW}}}$ , was investigated using a finite-element method simulation. The results show that the DBMTJ(A) and SBMTJ with the same MgO layer thickness of 0.9 nm provide a higher switching current, ${I}_{{\text {C}}}$ , than the DBMTJ(B) with a MgO layer thickness of 1.3 nm. The ${T}_{{\text {SW}}}$ in a DBMTJ(A) is higher than that in an SBMTJ, while ${T}_{{\text {SW}}}$ for a DBMTJ(B) is the smallest because of its low ${I}_{{\text {C}}}$ . The DBMTJ(A) and DBMTJ(B) can be applied in a higher temperature range than the SBMTJ at a $\Delta $ of 40. In addition, the STT efficiency factor, $\Delta /{I}_{{\text {C0}}}$ , for a DBMTJ is better than the factor for an SBMTJ. Although the temperature increment would cause an undesirable reduction in $\Delta $ , it can reach a low ${E}_{{\text {SW}}}$ for the requirement of a fast write access time. Therefore, the control device for increasing the ${T}_{{\text {in}}}$ in the MTJs is attractive and should be promoted in the advancement of memory technology.

Basic circuit element for the implementation of base-3 and base-4 algorithms realized by an asymmetric MgO-based double-barrier magnetic tunnel junction

We study the resistance states and spin dynamics in a Ag/Fe(8)/MgO(3)/Fe(8)/MgO(5)/Fe/Ag junction based on a first-principles scattering theory. Spin dynamics simulations show that up to four resistance states with noticeable difference can be achieved via manipulating the voltage bias scheme and the position of the reference magnetization. The study indicates possible multiple-valued logic applications in an asymmetric MgO-based double-barrier magnetic tunnel junction.

Compact Modeling of Perpendicular-Magnetic-Anisotropy Double-Barrier Magnetic Tunnel Junction With Enhanced Thermal Stability Recording Structure

As the basic storage unit of spin transfer torque magnetic random-access memory (STT-MRAM), the perpendicular magnetic anisotropy (PMA) magnetic tunnel junction (MTJ) has been extensively studied in recent years. Lowering the critical switching current and improving the data retention are two crucial pathways to optimize the performance of STT-MRAM. However, the conventional MTJ can merely achieve both. In this paper, we present a physics-based compact model of Ta/CoFeB/MgO PMA double-barrier MTJ (DMTJ) with enhanced thermal stability recording structure. Combination of double-barrier and synthetic double-free layers can heighten the STT effect and enhance the thermal stability simultaneously. A larger STT switching efficiency, compared with conventional MTJ, can thus be realized. The modeling results show great agreement with experimental results. A 1-bit magnetic full adder (MFA) based on DMTJ, as a hybrid logic-in-memory circuit example, has been designed and simulated to validate its functionality. This SPICE-compatible compact model will be useful for high-performance hybrid MTJ/CMOS circuit and system designs.

Magnon resonant tunneling effect in double-barrier insulating magnon junctions and magnon field effect transistor

We predict a magnonic resonant tunneling phenomenon in the double-barrier insulating magnon junctions of ${\text{FI}}_{1}/{\text{AFI}}_{1}/{\text{FI}}_{2}/{\text{AFI}}_{2}/{\text{FI}}_{3}$, where ${\text{FI}}_{(1,2,3)}$ and ${\text{AFI}}_{(1,2)}$ denote the ferromagnetic and antiferromagnetic insulating layers, respectively. Similar to electron tunneling in well-known double-barrier magnetic tunnel junctions, each antiferromagnetic insulator layer acts as an effective potential barrier for magnons due to its intrinsically large magnon-spectrum gap of the order of THz. Based on the magnon tunneling effect, we further propose a magnon field effect transistor that is capable of realizing a gate-tunable transmitted magnon flow by tuning the resonant tunneling via a gate electric field induced Dzyaloshinskii-Moriya interaction in the middle FI layer. The advantages of such transistors include their broadband frequency width ranging from GHz to THz at room temperature, high scalability, and intrinsic low dissipation without Joule heating loss.