Embedded Memories for Cryogenic Applications

Esteban Garzón,Marco Lanuzza,Adam Teman

doi:10.3390/electronics11010061

Abstract

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

Highlights

Academic Editor: Kris CampbellCryogenic electronics is an emerging approach to improve computer performance and deal with the static power consumption issue resulting from transistor scaling towards the end of Moore’s law [1,2,3]
The embedded memory technologies considered in this work are shown in Figure 2: (a) 6T-Static Random-Access Memory (SRAM), (b) two-transistor mixed gain cell nMOS-pMOS (2T nMOS write port (NW)-PR GC-eDRAM), and (c) STT-MRAM based on single-barrier magnetic tunnel junction (SMTJ) or double-barrier MTJ (DMTJ)
We investigated the impact of cryogenic temperatures on different embedded memory technologies

Summary

Introduction

Cryogenic electronics is an emerging approach to improve computer performance and deal with the static power consumption issue resulting from transistor scaling towards the end of Moore’s law [1,2,3]. The relatively large bitcell area of 6T-SRAM limits the overall on-chip memory density and the many leakage paths present in these memories limit the achievable power savings [16] To improve on these issues, other memory technologies like Gain-Cell embedded DRAMs (GC-eDRAMs) and spin-transfer torque magnetic RAMs (STT-MRAMs) were recently proposed as promising candidates for cryogenic computing applications [5,14,16]. Leveraging the thermal stability factor of MTJ devices has been considered as a promising alternative to build reliable, energy-efficient, and high density STT-MRAMs at 77 K While this was experimentally demonstrated for SMTJ-based STT-MRAM, as reported by Taiwan Semiconductor Manufacturing Company (TSMC) [14], a DMTJ-based.

Background

Simulation Analysis at Cryogenic Temperatures

Comparison Results

Conclusions