Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

Esteban Garzón,Marco Lanuzza,Ramiro Taco,Sebastiano Strangio

doi:10.3390/electronics10151756

Abstract

Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET- and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (<0.5 V), while showing energy savings of 50% and faster write switching of 60%.

Highlights

Spin-transfer torque magnetic random access memory (STT-MRAM) is an attractive solution for on-chip non-volatile memories with zero standby power [1,2,3,4,5,6,7]
All the memory bitcells are in standard connection (SC) configuration, i.e., the reference layer top (RLT) of the double-barrier magnetic tunnel junction (DMTJ) is connected to the access transistor/s
We explored the impact of using tunnel FET (TFET) instead of FinFETs in DMTJ-based

Summary

Introduction

Spin-transfer torque magnetic random access memory (STT-MRAM) is an attractive solution for on-chip non-volatile memories with zero standby power [1,2,3,4,5,6,7]. Thanks to the inherent non-volatility, compatibility with CMOS processes, relatively large endurance and, in particular, small area footprint and ability to operate at relatively low voltages, STT-MRAM has become a key memory candidate for future Internet of Things (IoT) applications, where energy-efficiency is a highly sought-after feature [1,8]. Another work presented in [4] shows that STT-MRAM based on FinFET technology, along with DMTJ devices with two reference layers, enables lower operating voltage, thanks to the reduced DMTJ switching current as compared to conventional SMTJ, while maintaining sufficiently high thermal stability, so as not to affect data retention time. When powered at 0.4 V, TFET-based memory bitcells consume less energy (about −50%) and present better performance (about +60%) under write operation, as compared to the FinFETbased implementation This is achieved while ensuring higher robustness against process variability.

Ultralow Voltage Transistors and STT-DMTJ

STT-MRAM BitCell Simulation and Benchmark

Design point:

Findings

Conclusions