Doping-less Tunnel FET Research Articles

A new approach for ammonia gas sensing using a source pocket dopingless tunnel FET with PANI catalyst

This article presents a new ammonia (NH3) gas sensor designed using a dopingless tunnel field effect transistor with a SiGe source pocket (SP-DLT) and investigates its sensitivity using a polyaniline (PANI) conducting polymer as the gate catalyst. PANI nanofiber has a greater specific surface area and a linked network structure, which increases its sensing performance as a catalyst. Combining an HfO2 gate dielectric and SiGe source pocket improves the drain current. The sensing film is deprotonated when the PANI conducting polymer is exposed to the gas, reducing the film’s resistance. As a result, more electron or proton transfer is possible, ensuring a more substantial interaction between the sensor and the analyte gas. This modulates the electrical characteristics and work function of the TFET. The sensor’s electrical performance is examined in terms of drain current, average subthreshold swing (SS), electric field, band-to-band tunneling rate (BTBT), and energy band diagram for an ammonia gas pressure (AGP) range of 10−12 torr to 10−9 torr. The sensitivity and selectivity of the proposed PANI-SP-DLT sensor in terms of different metrics, including drain current, average SS, current ratio, transconductance, and gain factor, are further investigated. The study is expanded to consider the impact of temperature affectability and the germanium mole fraction on current sensitivity performance. The Silvaco ATLAS device simulator is used for the brief simulation work for the developed gas sensor.

Analytical modeling and performance assessment of a Si(1-x) Ge(x) pocketed double-gate dopingless tunnel FET biosensor

An analytical model of a dielectric-modulated double-gate Tunnel FET (DM-DG-TFET) biosensor carrying a Si(1-x) Ge(x) pocket is presented in this paper. The model accounts for the dielectric modulation effect on the surface potential and drain current of the designed biosensor device. An insight into the device physics provides an overview of commanding electrostatics and electrical properties associated with the proposed biosensor. The neutral, as well as charged nature of biomolecules, is considered for modeling and simulation data. Furthermore, the sensitivity for both types of biomolecules is analyzed in terms of threshold voltage (Vth) and on-current (Ion). The modeled and simulated results are extensively studied and compared for their scrupulosity. It has been found that the simulated and modeled results are a close match with each other, and the developed model justifies the physics behind the proposed biosensor. This paper also includes the impact of the nature of biomolecules on various parameters such as threshold voltage, sensitivity metrics, etc.

Switching and photosensitive analysis of dopingless tunnel field effect transistor based on cladding layer concept

— In this paper, the switching and photo sensing analysis of cladding layer based dopingless Tunnel FET (CDL-TFET) has been examined under visible range of spectrum. Initially, the impact of cladding layer in DL-TFET on electrical parameter is observed by varying the source material and thickness of source region. Furthermore, CDL-TFET is used for photo sensing application under the light state at various wavelength of light incident. The various optical figure of merits (FoMs) like spectral sensitivity (Sn), Signal to noise ratio (SNR), Responsivity (R), and quantum efficiency (η) is extracted to realize the behavior of photosensor. The maximum value of Sn is 48, R of 0.74 (A/Watt), SNR of 68.8 dB, and η of 3 are obtained at λ = 300 nm. Further, impurity trap charge effects are also observed at the interface and bulk of TFET. Finally, a comparison table has been presented to signify the importance of cladding layer based DL-TFET photo sensor with existing literature.

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell.

A high-performance doping-less tunnel FET with pocketed architecture: proposal and analysis

In this paper, we propose a doping-less dual-material double-gate tunnel field-effect transistor with a P+ pocket (PP-DMG TFET). This gate-engineered technique is typically used in a MOSFET to improve device performance. The P+ pocket is embedded at the source side to enhance the performance of the pocket-engineered PP-DMG TFET device. This paper compares the performance of four DG-TFET-based devices, i.e. single-material gate (SMG), single-material gate with P+ pocket (PP-SMG), dual-material gate (DMG), and dual-material gate with P+ pocket (PP-DMG), by using 2D simulations. Electrostatic doping based on the charge plasma concept forms the requisite n–i–p+ structure for tunneling formed on a thin intrinsic silicon layer. The proposed device (PP-DMG) has high ON-current capability, a high ON/OFF ratio and lower point subthreshold of 15.3 mV/dec, and an average subthreshold of 18.6 mV/dec. The analog parameters transconductance (gm) and cutoff frequency (fT) show impressive improvement. The device efficiency and transconductance frequency product (TFP) are also discussed. Finally, linearity and distortion analysis of parameters including VIP2, VIP3, IIP3, and IMD3 is carried out.

Breast-Cancer Biomarker (C-erbB-2) Detection in Saliva/Serum Based on In1-xGaxAs/Si Hetero Junction Dopingless TFET Biosensor.

This research article reports the electrical detection of breast-cancer biomarker (C-erbB-2) in saliva/serum based on In1-xGaxAs/Si heterojunction dopingless tunnel FET (HJ-DL-TFET) biosensor for highly sensitive and real-time detection. The work takes into account the interface charge modulation effect in dopingless extended gate heterostructure TFET with embedded nanocavity biosensors for the precise, reliable, and fast detection of antigens present in the body fluids such as saliva in place of blood serum. The reported biosensor is numerically simulated in 2D using the SILVACO ATLAS exhaustive calibrated simulation framework. For the biomolecule immobilization, the proposed biosensor has a dual cavity engraved beneath the dual gate structure. This improves the control of biomolecules over the source-to-channel tunneling rate, as well as the control over the electrical performance parameters of the proposed biosensor. Here, a numerical model for the C-erbB-2 interface charge equivalent is also developed. The analysis of device sensitivity in both saliva and serum environments for various C-erbB-2 concentrations has been carried out. Our study reveals that III-V In1-xGaxAs/Si heterojunction with x composition of 0.2 and extended gate geometry provides an increased tunneling probability, improves the gate control to get a higher ION/IOFF ratio and higher sensitivity. In addition to this, the impact of interface charges corresponding to the different amounts of C-erbB-2 biomarkers on the biosensor sensitivity (in terms of ION/IOFF ratio) yields higher sensitivity of the order of 106.

Analysis and evaluation of Si(1-x) Ge(x) pocket on sensitivity of a dual-material double-gate dopingless tunnel FET label-free biosensor

This work reports a sensitivity analysis for a dual-material double-gate dopingless Tunnel FET (DM-DG-DLTFET) biosensor carrying a Si(1-x) Ge(x) pocket for improved performance of an overall device. The biomolecules are immobilized in a cavity suitable for small-sized biomolecules detection and the performance of the device is investigated by calculating the electrical properties altered due to the dielectric modulation caused by presence and absence of biomolecules by commercially available ATLASTM tool. The Si(1-x) Ge(x) pocket placed under the cavity at source-channel interface helps to attain better on-current which is usually less in case of other reported structures of Tunnel FETs. The variation in the composition of Ge is observed to obtain enhanced sensitivity. The device is studied for threshold voltage sensitivity of neutral as well as charged biomolecules and the nature of the present biomolecule is also determined using the transconductance-to-current ratio (gm/Ids) which can also be considered as a sensing metric. The optimized device design has been proposed keeping track of the electrical and physical trade-offs. Our results show a maximum of 539.5 mV shift in the threshold voltage when dielectric constant (K) of the neutral biomolecule is varied from 1 to 12 which makes our device evidently an efficient candidate for label-free biosensing application.

Performance investigation of Ge DLTFET based digital integrated circuit

ABSTRACT The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications.

Reliability analysis of cost-efficient CH3NH3PbI3 based dopingless tunnel FET

Electrostatically-doped TFETs (ED-TFETs) are amongst the most widely used cost-efficient steeper devices due to the use of charge-plasma technique and tunneling mechanism. However, the reliability analysis of ED-TFETs is considered an important concern for the research community. Most studies have only focused on improving the performance of ED-TFETs such as dopingless (DL)-TFET in terms of on-current (I ON), subthreshold swing (SS) and threshold voltage (V th), rather than investigating the reliability issues. In this context, the aim of our work is to investigate the reliability analysis of our previously reported methyl-ammonium lead tri-iodide materials based DL-TFET (MAPbI3-DL-TFET). The influence of interface trap charges, shallow and deep defects on the electrical and analog performance of MAPbI3-DL-TFET has been analyzed using the Silvaco ATLAS tool at room temperature. Extensive results produced show that deep-level (Gaussian) defects impact the performance of the device prominently while the tail defects affect the device performance insignificantly. The present findings showed that the donor/acceptor trap charges impact the device in the subthreshold region considerably, while in the superthreshold region the impact of trap charges is marginal. In our view, these results emphasize the reliability analysis of MAPbI3-DL-TFET for the very first time. We hope that our research will be useful and valuable for DL-TFET manufacturers.

Investigation of Charge-plasma Based Dopingless Tunnel FET for Analog/RF and Linear Applications

Investigation of Charge-plasma Based Dopingless Tunnel FET for Analog/RF and Linear Applications

Design and analysis of negative capacitance based dual material dopingless tunnel FET

In this paper, ferroelectric material based Dual Material Gate-Doping Less Tunnel Field Effect Transistor (DMG-DLTFET) is designed using gate stacked PZT to induce negative capacitance (NC) in the device and analyzed for various device parameters namely trans -conductance (g m ), drain current (I d ), subthreshold slope (SS), threshold voltage (V TH ) and Total capacitance (C T ). Simulated parameters are compared with conventional DMG-DLTFET and it has been found that NC based DMG-DLTFET gives better results. Furthermore, NC reduces the SS resulting in fast switching and hence low power consumption. The effect of thickness of the dielectric material PZT is presented which plays vital role in deciding negative capacitance in device. • Ferroelectric material based Dual-Material Gate-Dopingless Tunnel FET. • Simulated parameters are compared with conventional and NC based DMG-DLTFET gives better results. • Negative Capacitance reduces the SS resulting in fast switching and hence low power consumption.

A Raised Source/Drain Dopingless Tunnel FET with Stacked Source: Design and Analysis

In this paper, we propose a novel n-type raised source/drain dopingless tunnel field-effect transistor along with stacked source configuration. Using calibrated TCAD 2-D device simulations, we show that the proposed device has three order reduced ambipolar current due to the raised source/drain regions and improved subthreshold characteristics through the use of stacked source configuration (upper Ge/ lower Si source region) in comparison with conventional DLTFET. The raised upper Ge source layer enables vertical tunneling for excellent dc characteristics in terms of high ION/IOFF ~ 1011 ratio, and 2.5 times steeper average subthreshold swing without any increment in leakage current in contrast to conventional DLTFET. Moreover, the proposed device encapsulates the ingrained advantages of reduced fabrication complexity and high invulnerability towards random dopant fluctuations(RDFs) on account of the dopingless architecture using charge-plasma concept.

Numerical simulations of a novel CH3NH3PbI3 based double-gate dopingless tunnel FET

Tunnel field effect transistors (TFETs) are generating considerable interest in switching applications due to their steep-subthreshold slope achieved by the quantum mechanical tunneling as a switching mechanism. However, all TFET structures currently in vogue based on Si, Ge or III–V materials have not been able to satisfy the other stringent requirements like higher on current (I ON) and low cost of fabrication. We, in this paper, report a cost-effective, organic–inorganic hybrid perovskite CH3NH3PbI3 material-based DG–DL TFET (labeled as MAPbI3–DG–DL TFET hereinafter) which has been shown to adapt to the advantages of the double gate (DG) and doping less (DL) technique for better electrostatic control and low thermal budget respectively. In simulations conducted using Silvaco Atlas tool at room temperature and supply voltage of 1 V on the proposed device structure, we have been able to achieve subthreshold swing of 27.33 mV decade−1, cut-off frequency of 0.268 THz and switching ratio of 1.85 × 1011. Detailed explanations of the results provided in the paper tend to establish that MAPbI3–DG–DL TFET could be a suitable candidate for low-power and high-speed logic applications.

Analytical modeling analysis and simulation study of dual material gate underlap dopingless TFET

An analytical model of dual material single gate doping-less Tunnel FET (DM-GU-TFET) with gate underlap regions has been proposed. The potential of gate underlap area with channel area has been examined using modeling and the results are validated using TCAD simulation at boundary conditions. The proposed structure has been divided into ten distinct sections (counting source/drain depleted sections) to get potential models while settling the 1-Dimensional and 2-Dimensional Poisson equations (PE) condition in the respective sections. To settle the PE's at different limit conditions, explanatory estimate strategy is proposed and tested. The effect of geometric morphology, for instance under-lap length, has been analyzed, which is dependent on electrical attributes of DM-GU-TFET. The parabolic approximation technique is used to settle the PE's at various interface conditions. The effect of structural variations viz. gate underlap length and tunneling length is scrutinized using electrical characteristics of DM-GU-TFET. The resultant characteristics of proposed dopingless TFET represent a noteworthy improvement in surface potentials with variation in length of spacer region, underlap section and tunneling region.

Doping-Less Tunnel Field Effect Transistor Using Compact-Si-Drain, SiGe-Channel, and Ge-Source

Design rules of the conventional MOSFETs are continuously decreasing, along with the strong requirement of extremely low subthreshold swing level of more than 50 mV/dec at a sub-6-nm node1. As the MOSFET devices cannot meet the demands of key markets, such outstanding electrical features: low-power, high on/off ratio, low off-current, and high on-current, a quantum tunnel FET(TFET) have garnered considerable interest as a crucial alternative to overcome the above issues. However, The TFET has the disadvantages of introducing random dopants fluctuation(RDF) event initially caused by carrier diffusion in the channel region2. Thus, doping-less(DL)-TFET approach using a charge-plasma concept has become highly promising option for use in future TET research areas3,4. In this work, we address a novel device structure and practical fabrication procedure for the sub-10-nm TFET ensuring advanced am-bipolar and ON-state current behaviors on the basis of the well-known charge plasma concept.We experimentally fabricated and analyzed the conventional DL TFET (see Fig. 1(a)). The roughness of the gate oxide and the interface was high. (see Fig. 1(b)) As a result, the DL TFET showed relatively high am-bipolar and low ON-state current characteristics, as shown in Fig. 1(c). The proposed device includes a 3-nm-thick compact-drain(CD) for the efficient suppression of am-bipolar current and hetero-material(HM) of Si(drain)-SiGe(channel)-Ge(source) for the improved ON-state current, where a particular Ge-condensation process developed in our previous work is adapted for the formation of HM. The CD-HM-DL TFET starts with a thin SOI wafer and fin-type structure to facilitate the fabrication process, as seen in Fig. 1(d) and (e). The TCAD simulation findings imply that a silicon band-gap is highly dependent on the drain thickness owing to a quantum size effect and the band-gap energy is found to be a 1.27 eV at about 3-nm-thick silicon. In addition, the am-bipolar current of the 3-nm-thick CD-DL TFET provides an extremely low current (more than 160 times), when compared with that of a conventional doping-less(DL) TFET with 10-nm-thick drain, as displayed in Fig. 1(f). The HM-DL TFET based on the Si(drain)-SiGe(channel)-Ge(source) configuration exhibited a tunnel path of 2.1 nm at a gate voltage 1.5 V, which is 44.7 % lower than the conventional DL-TFET. The ON-state current of the HM-DL-TFET is 4.8 times higher than that of the conventional DL-TFET, as seen Fig. 1(g). When the compact Si-drain, SiGe-channel and Ge- source were applied, in particular, am-bipolar and ON-state characteristics were improved, as evident in Fig. 1(h). The results indicate that the proposed CD-HM-DL TFET may establish a useful and simple route for advanced electrical performance, such as suppressed am-bipolar current and increased ON-state current, which is possibly essential to the realization of low power and high performance applications by using a relatively small number of few fabrication steps. Figure caption Fig. 1. The conventional DL TFET and proposed CD-HM-DL TFET configuration and electrical characteristics (a) DL TFET schematics, (b) TEM Cross-sectional image, (c) I-V curve of DL TFET, (d) CD-HM-DL TFET schematics, (e) The AA’-line cross-sectional view, (f) band-gap energy with Si-thickness and I-V comparison of DL TFET with 3-nm-thick CD TFET (g) I-V comparison of DL TFET with Si(drain)-SiGe(channel)-Ge(source) HM TFET and (h) I-V comparison of DL TFET with CD-HM-DL TFET References J. Ahopelto, G. Ardila, L. Baldi, F. Balestra, D. Belot, G. Fagas, S. De Gendt, D. Demarchi, M. Fernandez-Bolaños, D. Holden, A.M. Ionescu, G. Meneghesso, A. Mocuta, M. Pfeffer, R.M. Popp, E. Sangiorgi, C.M. Sotomayor Torres, Solid State Electronics, vol. 155, pp 7-19, May 2019. doi: 10.1016/j.sse.2019.03.014.M.H. Chiang, J.N. Lin, K. Kim, C.T. Chuang, IEEE Transactions on Electron Devices, vol 54, No. 8, pp. 2055-2060, Aug 2007. doi: 10.1109/TED.2007.901154 R.J.E. Hueting, B. Rajasekharan, C. Salm, J. Schmitz, IEEE electron device letters, vol. 29 No. 12, pp. 1367-1369, Dec 2008. doi: 10.1109/LED.2008.2006864 4. M.J. Kumar, S. Janardhanan, IEEE Transactions on Electron Devices, vol 60, No. 10, pp. 3285-3290, Oct 2013. doi: 10.1109/TED.2013.2276888 Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2020, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

6-T and 7-T SRAM CELL Design Using Doping-Less Charge Plasma TFET

Charge plasma based doping-less tunnel FETs (DLTFETs) are attracting attention for providing reduced leakage currents and high ION/IOFF ratio. In this work, a new GaAs based gate stack charge plasma doping-less tunnel FET (GaAs based GSDLTFET) has been proposed. The simulation results show that the proposed device gives higher ION/IOFF ratio in comparison to DLTFETs due to high mobility of the GaAs substrate. Various SRAM circuits have been designed and analyzed using DLTFET and GaAs based GSDLTFET viz. 6 T standard SRAM, 6 T TFET SRAM and 7 T TFET SRAM. The circuit analysis shows that SRAM cell designed using GaAs based GSDLTFET provides better noise margins in comparison to DLTFET based SRAMs due to high ION/IOFF ratio. Standby leakage power is also reduced in DLTFETs as compared to CMOS. Due to the enhanced noise margins and reduced leakage power our proposed GaAs based GSDLTFET can be used to design energy- efficient memory devices.

A novel gate engineered L-shaped dopingless tunnel field-effect transistor

Recently, dopingless tunnel FET (DL-TFET) has emerged and gathered much attention, for it avoids the physical doping process and provides superior immunity against random dopant fluctuation. Nevertheless, it also suffers from low drive current and severe ambipolar effect. In order to overcome these problems, an L-shaped DL-TFET (LDL-TFET) with the gate engineering technique is proposed in this paper. In this device, the space between the source and the gate electrodes can be further optimized to reduce the tunneling distance, and hence boost the drive current. Also, without much fabrication difficulties, hetero-gate-dielectric (HGD) and tunneling gate (TG) structures can be utilized in the LDL-TFET. Benefiting from the modification of the band energy by HGD and TG, the source-channel tunneling distance is further reduced, while the drain-channel tunneling distance is enlarged. TCAD simulation results show that in comparison with planar DL-TFET (PDL-TFET), LDL-TFET offers better performance in terms of on-current, switch ratio, subthreshold slope, ambipolar current and RF parameters. It indicates that the LDL-TFET is a promising device for low-power RF and digital logic applications.

Label Free Detection of Biomolecules Using SiGe Sourced Dual Electrode Doping-Less Dielectrically Modulated Tunnel FET

In this work, the performance of a Si0.5Ge0.5 sourced dual electrode doping-less Tunnel FET (DEDLTFET) biosensor using dielectric modulation is studied for different cavity length, thickness (Tbio) and charge densities (QF). The use of silicon-germanium (SiGe) based source also shows an improvement in the performance of the charge plasma Tunnel FET because of its enhanced drain current. Biomolecules are introduced inside the cavity region and their impact on the drain current has been investigated to design the biosensor. The sensitivity factor of the biosensor depends upon the drain current obtained which is proportional to the dielectric constant (k) and the charge density of the biomolecules. The proposed biosensor achieves a maximum drain current sensitivity of 7.7 × 108 at a cavity length of 25 nm and 2.7 × 109 at a cavity length of 30 nm. When compared with the conventional TFET biosensors, it is observed that Si0.5Ge0.5 sourced doping-less TFET biosensor provides better drain current sensitivity.

A novel Ge based overlapping gate dopingless tunnel FET with high performance

In this letter, the overlapping gate dopingless tunnel field-effect transistor (OGDL-TFET) is proposed and studied by TCAD simulation. To increase the tunneling efficiency and reduce the manufacture difficulty, a dopingless germanium tunneling junction based on charge plasma concept is induced in OGDL-TFET. A high efficiency line tunneling junction is formed by the gate/backgate overlap. The on-state current of 75.5 μA μm−1 and subthreshold swing of 1.9 mV/dec can be obtained. With cut-off frequency of 16.53 GHz and gain bandwidth product of 2.44 GHz, OGDL-TFET obtains good analog and radio frequency performance. The considerable good performance makes OGDL-TFET very attractive for ultra-low power application.

Impact of interface trap charges on dopingless tunnel FET for enhancement of linearity characteristics

For the first time, we have explored the effect of positive and negative interface trap charges on the dopingless device using charge plasma concept and named the proposed device as heterogeneous gate dielectric charge plasma tunnel field-effect transistor (HD-CP-TFET). The heterogeneous gate dielectric is considered to improve the ON-state current and device performance. The main intention of this work is to improve the drain current, transconductance characteristics along with linearity figure-of-merits (FOMs). A comparative analysis is done with conventional CP-TFET in the presence of interface trap charges (ITCs). From comparative results, it is found that the proposed device shows a better performance in the presence of interface trap charges. All the simulations are performed on ATLAS TCAD device simulator. The results show that the proposed device has a better tunneling current, transconductance (\(g_{\text {m}}\)), cut-off frequency (\(f_{\text {T}}\)), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3), and third-order intermodulation distortion (IMD3). Thus, the proposed device (HD-CP-TFET) shows the better performance in the presence of interface trap charges and indicates that this device is suitable for low-voltage analog/RF applications.