A Raised Source/Drain Dopingless Tunnel FET with Stacked Source: Design and Analysis

Abstract

In this paper, we propose a novel n-type raised source/drain dopingless tunnel field-effect transistor along with stacked source configuration. Using calibrated TCAD 2-D device simulations, we show that the proposed device has three order reduced ambipolar current due to the raised source/drain regions and improved subthreshold characteristics through the use of stacked source configuration (upper Ge/ lower Si source region) in comparison with conventional DLTFET. The raised upper Ge source layer enables vertical tunneling for excellent dc characteristics in terms of high ION/IOFF ~ 1011 ratio, and 2.5 times steeper average subthreshold swing without any increment in leakage current in contrast to conventional DLTFET. Moreover, the proposed device encapsulates the ingrained advantages of reduced fabrication complexity and high invulnerability towards random dopant fluctuations(RDFs) on account of the dopingless architecture using charge-plasma concept.