Doping-Less Tunnel Field Effect Transistor Using Compact-Si-Drain, SiGe-Channel, and Ge-Source

Abstract

Design rules of the conventional MOSFETs are continuously decreasing, along with the strong requirement of extremely low subthreshold swing level of more than 50 mV/dec at a sub-6-nm node1. As the MOSFET devices cannot meet the demands of key markets, such outstanding electrical features: low-power, high on/off ratio, low off-current, and high on-current, a quantum tunnel FET(TFET) have garnered considerable interest as a crucial alternative to overcome the above issues. However, The TFET has the disadvantages of introducing random dopants fluctuation(RDF) event initially caused by carrier diffusion in the channel region2. Thus, doping-less(DL)-TFET approach using a charge-plasma concept has become highly promising option for use in future TET research areas3,4. In this work, we address a novel device structure and practical fabrication procedure for the sub-10-nm TFET ensuring advanced am-bipolar and ON-state current behaviors on the basis of the well-known charge plasma concept.We experimentally fabricated and analyzed the conventional DL TFET (see Fig. 1(a)). The roughness of the gate oxide and the interface was high. (see Fig. 1(b)) As a result, the DL TFET showed relatively high am-bipolar and low ON-state current characteristics, as shown in Fig. 1(c). The proposed device includes a 3-nm-thick compact-drain(CD) for the efficient suppression of am-bipolar current and hetero-material(HM) of Si(drain)-SiGe(channel)-Ge(source) for the improved ON-state current, where a particular Ge-condensation process developed in our previous work is adapted for the formation of HM. The CD-HM-DL TFET starts with a thin SOI wafer and fin-type structure to facilitate the fabrication process, as seen in Fig. 1(d) and (e). The TCAD simulation findings imply that a silicon band-gap is highly dependent on the drain thickness owing to a quantum size effect and the band-gap energy is found to be a 1.27 eV at about 3-nm-thick silicon. In addition, the am-bipolar current of the 3-nm-thick CD-DL TFET provides an extremely low current (more than 160 times), when compared with that of a conventional doping-less(DL) TFET with 10-nm-thick drain, as displayed in Fig. 1(f). The HM-DL TFET based on the Si(drain)-SiGe(channel)-Ge(source) configuration exhibited a tunnel path of 2.1 nm at a gate voltage 1.5 V, which is 44.7 % lower than the conventional DL-TFET. The ON-state current of the HM-DL-TFET is 4.8 times higher than that of the conventional DL-TFET, as seen Fig. 1(g). When the compact Si-drain, SiGe-channel and Ge- source were applied, in particular, am-bipolar and ON-state characteristics were improved, as evident in Fig. 1(h). The results indicate that the proposed CD-HM-DL TFET may establish a useful and simple route for advanced electrical performance, such as suppressed am-bipolar current and increased ON-state current, which is possibly essential to the realization of low power and high performance applications by using a relatively small number of few fabrication steps. Figure caption Fig. 1. The conventional DL TFET and proposed CD-HM-DL TFET configuration and electrical characteristics (a) DL TFET schematics, (b) TEM Cross-sectional image, (c) I-V curve of DL TFET, (d) CD-HM-DL TFET schematics, (e) The AA’-line cross-sectional view, (f) band-gap energy with Si-thickness and I-V comparison of DL TFET with 3-nm-thick CD TFET (g) I-V comparison of DL TFET with Si(drain)-SiGe(channel)-Ge(source) HM TFET and (h) I-V comparison of DL TFET with CD-HM-DL TFET References J. Ahopelto, G. Ardila, L. Baldi, F. Balestra, D. Belot, G. Fagas, S. De Gendt, D. Demarchi, M. Fernandez-Bolaños, D. Holden, A.M. Ionescu, G. Meneghesso, A. Mocuta, M. Pfeffer, R.M. Popp, E. Sangiorgi, C.M. Sotomayor Torres, Solid State Electronics, vol. 155, pp 7-19, May 2019. doi: 10.1016/j.sse.2019.03.014.M.H. Chiang, J.N. Lin, K. Kim, C.T. Chuang, IEEE Transactions on Electron Devices, vol 54, No. 8, pp. 2055-2060, Aug 2007. doi: 10.1109/TED.2007.901154 R.J.E. Hueting, B. Rajasekharan, C. Salm, J. Schmitz, IEEE electron device letters, vol. 29 No. 12, pp. 1367-1369, Dec 2008. doi: 10.1109/LED.2008.2006864 4. M.J. Kumar, S. Janardhanan, IEEE Transactions on Electron Devices, vol 60, No. 10, pp. 3285-3290, Oct 2013. doi: 10.1109/TED.2013.2276888 Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2020, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1