Channel Doping Research Articles

Tunable photo-response in the visible to NIR spectrum range of Germanium-based junctionless nanowire transistor

In this paper, the phototransistor behavior is investigated in the germanium-on-insulator (GeOI)-based junctionless nanowire (JL-NW) transistor under various light conditions. High responsivity and photosensitivity are attributed in the fully depleted regime within the visible and near-infrared bands. The impact of light is also investigated in detail on the electronic and transfer characteristics such as energy bandgap, carrier distribution, electrostatic potential, electric field, generation and recombination rates. Further, the channel doping and thickness are tuned to optimize the optical responsivity. The significant tunability of responsivity is observed with increasing channel thickness. The device exhibits fast optical switching performance, which is further enhanced at higher input light power. Overall, at the nanoscale dimension, our proposed phototransistor demonstrates better detectivity with a significantly smaller illumination area. Thus, the GeOI-based JL-NW phototransistors can be used for imaging (visible wavelength range) and bioimaging (near-infrared wavelength range) applications in advanced technology nodes.

Numerical Modelling of Carrier Transport in Organic Field Effect Transistors

Background: Organic field effect transistors (OFETs), used in the fabrication of nanosensors, are one of the most promising devices in organic electronics because of their lightweight, flexibility, and low fabrication cost. However, the optimization of such OFETs is still in an early stage due to the minimal analytical and numerical models presented in the literature. Objective: This research presses to demonstrate a numerical carrier transport model based on the finite element method (FEM) to investigate the I-V characteristic of OFETs. Methods: Two various organic semiconductor materials have been included in the study, polyaniline and pentacene, where micro-scale, as well as nano-scale models have been presented. OFETs regarding channel length, dielectric thickness, and doping level impact have been studied. We nominated the threshold voltage, the on/off current ratio, the sub-threshold swing, and the field effect mobilities as the primary output evaluating parameters. Results: The numerical model has shown the criticality of the doping effect on tuning the device flowing drain current to exceed 300 μA saturation current, along with a threshold voltage of -0.1 V under a channel length of 30 nm. Conclusion: The study highlights the effectiveness of polyaniline over pentacene as nano-channel length OFET due to the boosted conductivity of polyaniline concerning pentacene.

Linearity analysis of FE-based graded channel junctionless FET obtaining negative capacitance for low power applications

This paper reports ferroelectric (FE) oxide based graded-channel junctionless FET featuring the negative capacitance effects in nano-scale regime. The linearity nature of its response is analysed on the basis of third order interception point (PIP3), harmonic interception voltages of 2nd and 3rd orders (VIP2, VIP3) and intermodulation distortion (IMD3). Influence of fundamental device’s parameters such as, gate and underlap length, ferroelectric oxide thickness, graded channel doping and operating temperature on its linear behavior is observed and analysed in detail. The subthreshold slope is also found to go below 60mV/dec for optimum features, obtaining the NC characteristics. In its circuit application part, a cascode amplifier is designed using the proposed device showing variations due to the change in the proposed device dimensions. The proposed device is designed and simulated using Silvaco ATLAS device simulator, which is calibrated with the available experimental results. Therefore, the present study is quite relevant in recent days for low power analog applications.

High-performance InGaZnO power transistors: Effect of device structural parameters

In this work, the effect of offset channel length (Loffset) and the dielectric layer thickness (d) on the InSnO/InGaZnO (ITO/IGZO) dual-active-layer (DAL) high-voltage thin-film transistors (HV-TFTs) is systematically investigated. The characteristics of the DAL HV-TFTs resemble that of GaN high electron mobility transistors, wherein the breakdown voltages (VBD) reach saturation at a certain Loffset, and the on-resistance (Ron) linearly increases with Loffset. The linear fitting of Ron vs Loffset indicates that d has a multifaceted impact on the performance of HV-TFTs. In addition to its theoretical role in transistor models, d also influences the channel doping concentration and sidewall deposition issues in practical devices. The DAL HV-TFT with a 30-nm Al2O3 gate dielectric achieves a remarkable VBD of 450 V, the highest figure of merit of 118.2 kW/cm2, and a positive threshold voltage of 3.65 V. Both experiments and simulations indicate that the breakdown occurs within the semiconductor channel, paving the way for further improvement of the performance.

Sputter-Deposited copper iodide thin film transistors with low Operating voltage

This paper reports on a back-gated p-type thin film transistor (TFT) with copper iodide (CuI) as the channel material, a HfO2 gate dielectric layer, and Al2O3 passivation. The γ-CuI channel was deposited from a CuI target using DC magnetron sputtering at room temperature. Our TFT can be fully shut off by VG = 4 V, with a field-effect channel hole mobility μh ∼ 1.5–2 cm2 V−1 s−1. An anneal in forming gas was performed twice, once at 200 °C, then at 250 °C to improve gate control, yielding a final Ion/Ioff current ratio of ∼ 250. The anneal served two purposes: to reduce the oxygen acceptor density in the CuI channel and reduce the concentration of interface states between the CuI, Al2O3 passivation, and HfO2. A model of the device was built in an industrial TCAD simulator, which reproduces the measured characteristics and allows an estimation of interface state densities and channel doping.

Exploring Neuromorphic Computing with Double-Gate Floating Device Based on Van Der Waals Heterostructures

Neuromorphic devices represent a frontier in technological development, aiming to emulate the intricate parallel functionalities inherent to the human brain [1, 2]. Traditional computing models, such as Von Neumann architecture, grapple with limitations in parallel processing, prompting the exploration of neuromorphic computing to integrate memory and processing efficiently. Our research presents the double gate floating device based on Vander Waals heterostructure (DG-VH-FET), employing molybdenum disulfide (MoS2), hexagonal boron nitride (h-BN), and graphene (Gr) as key components. These devices, based on 2D materials, enable independent modulation of channel doping through electrostatic means [3].In this study, we initially assessed the fundamental characteristics of the floating gate, including transfer characteristics, output characteristics, retention, and endurance. By applying constant drain-to-source voltages (VDS) while introducing variations in the back gate voltage (VBG) sweeping range, the memory window of the transfer characteristics changes. Conversely, maintaining a constant VBG and VDS while varying the top gate voltage (VTG) solely results in a shift in the threshold voltage of the memory window. This is attributed to the crucial role of VBG in charge trapping in the floating gate layer, with the influence of VTG on charge trapping being negligible due to the screening effect of MoS2 [4]. Moreover, by using VTG and VBG this study shows that DG-VH-FET could have potential applications in exploring and understanding various neurological effects, thereby bridging the gap between electronics and biology. Figure 1

A Comprehensive Analysis of Nanosheet Field-Effect Transistor: Recent Advances and Comparative Study

In this paper for the first time, we have studied various structures of nanosheet field-effect transistors (NSFET) and the effect of various devices and process parameters such as nanosheet width, length, interspacing, S/D doping, channel doping, random dopant fluctuations studied on these device structures. Comparative analysis has been done between JL-NSFET, GS-JL-NSFET, JL-SiGeNSFET and JL-GS-SiGeNSFET in terms of analog parameters. Nanosheet-based FETs are likely to be the successor of FinFET beyond the 5-nm node. NSFETs have better control over gate, variable sheet width and more current per device footprint which gives them the advantage of circuit design versatility. NSFET offers better gate control, better current and switching per device footprint. NSFETs are preferred over NWFETs due to better electrostatics, greater channel widths, decreased SCEs and increased device reliability.

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

The purpose of this study is to investigate the possibilities of the junction-less double-gate (JLDG) MOSFET structure with gallium nitride (GaN) channel material to overcome the limitations of conventional MOSFET structures in improving device performance at scaled gate lengths and voltages. The design targets of this study are the doping profile (ND), and gate work function (Ф). The device has been modeled using the Silvaco Atlas 2D device simulator. The proposed model has been validated by calibrating it against the parabolic potential-based analytical model for short-channel JLDG MOSFETs in the subthreshold regime of Jazaeri et al. Device figure of merits (FOMs) such as ON-current (ION), ON-OFF current ratio (ION/IOFF), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) have been evaluated. The maximum on-current, (ION) = 0.9 mA/μm, has been achieved by tuning the channel doping concentration (ND) to 1 × 1019 cm−3. Tuning the gate work function, (Ф) also has a substantial effect on the behavior of the device. The lowest OFF-state current (IOFF) of 1.24 × 10−16 A/μm and power dissipation of 9.69 × 10−17 W/μm have been found for gate work-function (Ф) = 5.1 eV (Au). In addition, the on-current to off-current ratio (ION/IOFF) of 7.56 × 1012 revolutionizes the applicability of the device in the semiconductor industry. Thus, the remarkable improvements in device FOMs prove that GaN-based JLDG MOSFETs are a strong contender for applications requiring low-power logic switching in the next generation.

Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications

Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications

Reduction of off-state drain current in AlN/[formula omitted] HEMT by trap state engineering

In this work, we report various strategies to reduce the off-state drain leakage current (IOFF) in AlN/β−Ga2O3 high electron mobility transistor (HEMT) by 2D device simulation. We have investigated the effect of access region, channel doping concentration, barrier layer thickness, and trap state engineering on IOFF. The formation of a parallel channel deep into the substrate has been found to be responsible for large IOFF. All other strategies except trap state engineering have an incremental effect on IOFF. However, the device’s IOFF was reduced by around 12 orders of magnitude by trap-state engineering. Simultaneously, the on-state performance was unaffected, resulting in an elevated ION/IOFF current ratio of (1013). A steep subthreshold slope of 0.267 (V/dec) was also obtained. Further, we have investigated the impact of both donor- and acceptor-type traps on subthreshold characteristics. These promising results highlight the potential of AlN/β−Ga2O3 HEMT as a switch and for future high-power nanoelectronics applications.

Enhanced performance in doped micro-nano porous organic thin-film transistors

Molecular doping, as an effective technique for controlling the electrical property of organic semiconductors (OSCs) by introducing additional charges, has been proven to adjust important device parameters in organic thin-film transistors (OTFTs). Doping highly crystalline OSCs without disrupting structural order is a crucial challenge, as it significantly affects the charge carrier mobility. Here, we demonstrate a molecular doping method without disrupting the molecular ordering to improve the charge carrier mobility of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) based OTFTs via a simple thermal spin-coating method. The key is to introduce micro-nano pores into C8-BTBT thin-film for channel doping, which is achieved by mixing with the unsubstituted BTBT as it can be easily removed from the thin-film through an ordinary annealing process. Micro-nano pores allow the dopant molecules (2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane, F4-TCNQ) to access the conductive channel of OTFT, which is beneficial for charge injection. Indeed, we further discover that F4-TCNQ doped porous C8-BTBT thin-films exhibit better charge mobility than those of neat and F4-TCNQ doped C8-BTBT films in OTFTs. This work proposes an effective way to expose OSC conjugated core to the dopant, which not only improves the charge transfer reaction between organic/dopant semiconductor through cofacial stacking, but also reduces the trap density and contact resistance.

Gate Electrode Work Function Engineered Nanowire FET with High Performance and Improved Process Sensitivity

MOSFETs have been used in integrated circuits for a long time. These were replaced by FinFET’s in 2011. But for short-channel devices, FinFET’s have low performance due to various effects like velocity saturation, hot carrier effect, drain-induced barrier lowering, channel length modulation, fringing field effect, sub-threshold conduction, threshold voltage roll-off, etc. Gate All Around FET (GAA FET) is the best device that will replace the FinFET’s. Therefore, during the fabrication process, it is crucial to investigate the effects of process variations caused by changes in device dimensions. This research discusses the performance of the proposed device due to process variations. The effect of changes in radius, gate oxide thickness, gate length, and channel doping on GAA FET has been discussed in detail.

Integration of Machine Learning with Statistical Variation Analysis for Ferroelectric Transistor (FE-MOSFETs)

This paper investigates a comparative analysis of technology computer-aided design (TCAD) versus machine learning (ML) technique for ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET), which shows the low power energy storage device and ML algorithms reduce the time or overall process. The simulations carried out through TCAD require approximately 44–46 days, encompassing variations in input parameters like gate work function ([Formula: see text]), doping concentration ([Formula: see text]), channel doping ([Formula: see text]), gate-to-source voltage ([Formula: see text]), and drain-to-source voltage ([Formula: see text]). In order to lower the computing cost of numerical TCAD device simulations, a new ML-assisted technique is provided for studying the FE-MOSFET. To reduce the runtime of physics-based TCAD by about 10–12[Formula: see text]h for each iteration, a ML-based prediction alternative is created. The proposed combination of TCAD device simulation and ML algorithms is the future of the next generation of electronics.

2D MXene electrochemical transistors.

The solid-state field-effect transistor, FET, and its theories were paramount in the discovery and studies of graphene. In the past two decades another transistor based on conducting polymers, called organic electrochemical transistor (ECT), has been developed and largely studied. The main difference between organic ECTs and FETs is the mode and extent of channel doping; while in FETs the channel only has surface doping through dipoles, the mixed ionic-electronic conductivity of the channel material in organic ECTs enables bulk electrochemical doping. As a result, organic ECTs maximize conductance modulation at the expense of speed. To date ECTs have been based on conducting polymers, but here we show that MXenes, a class of 2D materials beyond graphene, enable the realization of electrochemical transistors (ECTs). We show that the formulas for organic ECTs can be applied to these 2D ECTs and used to extract parameters like mobility. These MXene ECTs have high transconductance values but low on-off ratios. We further show that conductance switching data measured using ECT, in combination with other in situ-ex situ electrochemical measurements, is a powerful tool for correlating the change in conductance to that of the redox state, to our knowledge, this is the first report of this important correlation for MXene films. 2D ECTs can draw great inspiration and theoretical tools from the field of organic ECTs and have the potential to considerably extend the capabilities of transistors beyond those of conducting polymer ECTs, with added properties such as extreme heat resistance, tolerance for solvents, and higher conductivity for both electrons and ions than conducting polymers.

Large-Scale Vertically Interconnected Complementary Field-Effect Transistors Based on Thermal Evaporation.

With the rapid development of integrated circuits, there is an increasing need to boost transistor density. In addition to shrinking the device size to the atomic scale, vertically stacked interlayer interconnection technology is also an effective solution. However, realizing large-scale vertically interconnected complementary field-effect transistors (CFETs) has never been easy. Currently-used semiconductor channel synthesis and doping technologies often suffer from complex fabrication processes, poor vertical integration, low device yield, and inability to large-scale production. Here, a method to prepare large-scale vertically interconnected CFETs based on a thermal evaporation process is reported. Thermally-evaporated etching-free Te and Bi2S3 serve as p-type and n-type semiconductor channels and exhibit FET on-off ratios of 103 and 105, respectively. The vertically interconnected CFET inverter exhibits a clear switching behavior with a voltage gain of 17 at a 4 V supply voltage and a device yield of 100%. Based on the ability of thermal evaporation to prepare large-scale uniform semiconductor channels on arbitrary surfaces, repeated upward manufacturing can realize multi-level interlayer interconnection integrated circuits.

Tri-gate junctionless transistors with electrostatically highly doped channel

Multiple-gated junctionless transistors (JLTs) with an extremely simple structure and bulk-conduction-based operation could overcome fundamental problems with respect to short-channel effects for sub-3-nm technology nodes. In this paper, the performance of a tri-gate JLT with an electrostatically highly doped channel is demonstrated through numerical simulation. Unique characteristics previously reported in fabricated JLTs were exhibited by the tri-gate transistors with an additional bottom-gate bias (Vgb = 50 V), which induced an effectively highly doped state of the channel. The results of this study show the feasibility of producing impurity scattering-free JLTs for next-generation technology nodes.

Implementation of source extended multiple field plates and asymmetric doping on β-Ga2O3 MOSFET for high power applications

In the present work, source extended multiple field plate design is implemented on β – Ga2O3 MOSFET and asymmetric doping design has been adopted in the channel such that higher doping is present at the source side and lower doping is considered at the drain side to achieve superior performance for power applications. Extensive numerical simulations using TCAD Silvaco have been conducted and the optimization of various critical parameters of the proposed device, including the number and lengths of field plates and channel doping, has been undertaken to achieve superior power performance. Further, a comparison is drawn between the proposed device with (i) the device with multiple field plates at the source side and uniform channel doping, and (ii) the conventional device (without field plates and asymmetric channel doping) in terms of various critical attributes such as ON-state resistance, drain current, transconductance, breakdown voltage and power figure of merit etc. The present study demonstrates that the proposed device yields not only a remarkable improvement of 261 % in breakdown voltage and a substantial improvement in PFoM of 1120 % but also delivers higher drain current and peak transconductance when compared to the other devices under consideration. Additionally, the performance of all devices has been investigated at elevated temperatures and it has been found that the proposed device is well-suited for high-temperature applications as well since least degradation in drain current at higher temperatures is observed for the proposed device.

Achievement of extremely small subthreshold swing in Vertical Source-All-Around-TFET with suppressed ambipolar conduction

In this manuscript, we come up with a new line-tunneling-based channel-engineered GaAsSb/GaSb heterojunction Source-All-Around Vertical Nanowire TFET (SAA-NW-VTFET) and analyzed by Sentaurus TCAD-3D simulation. In this proposed model, increased tunneling area at the source-channel interface and the n+-pocket region, along with selective III-V compound semiconductors, have boosted the ON-current in the device. On the other hand, non-uniform channel doping and reduced tunneling area at the drain end have significantly suppressed the ambipolar current. The significant results in terms of ON-current (ION = 0.789 × 10−4 A/μm), OFF-current (IOFF = 1.08 × 10−17 A/μm), ION/IOFF ratio (7.25 × 1012), threshold voltage (0.2 V), point subthreshold swing (SS = 3 mV/dec) and average SS (SSavg = 7 mV/dec) are obtained in the simulation study. In addition, the effect of temperature (250 K–450 K) on device DC characteristics and DIBT is also presented.

Simulation study of total ionizing dose effect of gamma radiation on 15 nm bulk FinFET

FinFET is a new mainstream semiconductor device that is widely used in space applications. This paper studies the effects of radiation damage typically encountered in space applications by simulating the effects of total ionizing dose (TID) from 0 to 1 Mrad on a 15 nm n-type bulk FinFET. In particular we have simulated the effects of radiation damage on the transfer characteristic curve, threshold voltage and subthreshold swing of the FinFET. We have also varied some device process parameters such as gate length, fin width and fin height in order to assess their impact on the device susceptibility to radiation damage and our results show that the device structure with longer gate length, wider fin width and taller fin height have better performance. In addition, the higher channel doping concentration, the use of SiO2 in the gate, and the low device operating temperature can also effectively reduce the TID effects.

Fin field-effect-transistor engineered sensor for detection of MDA-MB-231 breast cancer cells: A switching-ratio-based sensitivity analysis.

The present study describes the utilization of a gallium-arsenide gate-stack gate-all-around (GaAs-GS-GAA) fin field-effect transistor (FinFET) to accomplish the electrical identification of the breast cancer cell MDA-MB-231 by monitoring the device switching ratio. The proposed sensor uses four nanocavities carved beneath the gate electrodes for enhanced detection sensitivity. MDA-MB-231 (cancerous) and MCF-10A (healthy) breast cells have a distinct dielectric constant, and it changes when exposed to microwave frequencies spanning across 200 MHz and 13.6 GHz, which modifies the electrical characteristics, allowing for early diagnosis. First, a percentage shift in the primary DC characteristics is presented to demonstrate the advantage of GS-GAA FinFET over conventional FinFET. The sensor measures the switching-ratio-based sensitivity, which comes out to be 99.72% for MDA-MB-231 and 47.78% for MCF-10A. The sensor was tested for stability and reproducibility and found to be repeatable and sufficiently stable with settling times of 55.51, 60.80, and 71.58 ps for MDA-MB-231 cells, MCF-10A cells, and air, respectively. It can distinguish between viable and nonviable cells based on electrical response alterations. The possibility of early detection of cancerous breast cells using Bruggeman's model is also discussed. Further, the impact of biomolecule occupancy and frequency variations on the device sensitivity is carried out. This study also explains how to maximize the sensing performance by adjusting the fin height, fin width, work function, channel doping, temperature, and drain voltage. Lastly, this article compared the proposed breast cancer cell detectors to existing literature to evaluate their performance and found considerable improvement. The findings of this research have the potential to establish GaAs-GS-GAA FinFET as a promising contender for MDA-MB-231 breast cancer cell detection.