DMOS Transistors Research Articles

A Physics-Based Compact Model to Capture Cryogenic Behavior of LDMOS Transistors

In this work, a detailed characterization of lateral DMOS transistors in the cryogenic regime is carried out. It is shown that carrier freeze-out in the drift region is responsible for increased ON-resistance for temperatures lower than a transition temperature, which is independent of device dimensions. The carrier freeze-out affects the operation of laterally diffused MOS (LDMOS) transistors in the linear region but not in the saturation region due to field-assisted ionization. A peak behavior in output conductance is also observed at cryogenic temperatures. The physics behind these observed anomalous behaviors is studied in detail and modeled. The industry-standard HiSIM_HV2 model is augmented with new equations to extend the model accuracy to 77 K. The accuracy of the model is verified with the data measured from LDMOS transistors with different dimensions. The model accurately captures the device behavior in the 77–300 K temperature range and demonstrates excellent scalability.

Оценка влияния структурных особенностей кристалла на стойкость ДМОП транзисторов к ионизирующему излучению

The work is devoted to the study of the influence of the structural features of the crystal on the resistance of DMOS transistors under the influence of ionizing radiation. A comparison of the results of instrumentation and technological modeling of commercially available p-channel DMOS transistors designed for the maximum allowable drain-source voltage of 60V and 100V is carried out. Modeling was carried out in the TCAD environment, all the basic physical principles of the structure under study were taken into account with the help of appropriate mathematical models. The obtained values of the model's electrical parameters showed full compliance with the normative values. The critical points of the crystal design that affect the performance of transistors in the presence of ionizing radiation from outer space are determined. The influence of the electric field strength in the crystal body on the resistance to ionizing radiation is estimated. It is shown that the actual values of the electric field strength in the region of the p-n junction do not exceed the values of the critical strength, having a margin of more than 1.22 times.

Test Structure Design for Defect Detection during Active Thermal Cycling.

Integrated power ICs acting as smart power switches for automotive or industrial applications are often subjected to active thermal cycling. Consequently, they undergo significant self-heating and are prone to various failure mechanisms related to the electro-thermo-mechanical phenomena that take place in the device metallization. In this article a test structure consisting of a lateral DMOS transistor equipped with several integrated sensors is proposed for metallization fatigue assessment. The design of the test structure is presented in detail, alongside with design considerations drawn from the literature and from simulation results. The testing procedure is then described, and experimental results are discussed. The experimental data provided by the integrated sensors correlated with the electro-thermal simulation results indicate the emergence of a failure mechanism and this is later confirmed by failure analysis. Conclusions are further drawn regarding the feasibility of using the proposed integrated sensors for monitoring defects in power ICs.

A Steady-State LDMOST Model Based on Semi-Numerical Regional Approach

This paper presents a high-voltage lateral DMOS transistor (LDMOST) model for steady-state condition.The device modelling method is basically based on a semi-numerical regional approach.The complete model is physical, so that it accounts for unique LDMOST features such as non-uniform channel doping, non-planar drift region and space-charge-limited current flowing.Themodelcalculationsshow good overall agreement withthe measured results.This DMOS transistor model, whichcan beapplicable to a SPICE-like circuit simulator, might be useful in technology CAD of high-voltage power ICs.

The Influence of Repetitive UIS on Electrical Properties of Advanced Automotive Power Transistors

This paper investigates a degradation of three types of automotive power MOSFETs through repetitive Unclamped Inductive Switching (UIS) test typically used to evaluate the avalanche robustness of power devices. It is not uncommon in switching applications that greater than the planned voltage for voltage spikes can occur, so even the best electronic designs may encounter frequent avalanche events. Hence, there is a need to analyse the impact of repetitive avalanching on the electrical performance of power transistors. This article focused on the shift of main electrical parameters: on-resistance R_{ON}, breakdown voltage V_{BR}, threshold voltage V_{TH}, and corresponding characteristics, as well as capacitances. Analysis proved that DMOS transistors are less vulnerable to repetitive avalanching. The most impacted parameter was on-resistance R_{DSon}, where a 14 % increase was observed after 6 x 10^7 stress pulses. The parameters shift is attributed to hot carrier injection in the space charge region of blocking PN junction and involves mainly defects generation/activation in the drain side region of the gate oxide. For the TrenchMOS transistor, a significant shift of I-V curves was observed with considerable impact on the R_{ON} where an increase of 22 % was observed. The trench corner is verified to be the mainly degraded region by Synopsys Technology Computer Aided Design (TCAD) simulations. Degradation of drain-gate capacitance C_{DG} and input capacitance C_{in} was observed in all three types of analysed structures. DLTS was used to verify the generation/activation of defects invoked by stress. An increase of DLTS signal corresponding to energy levels of oxygen vacancies and impurities in SiO_2 and on interfaces were detected on stressed samples.

Hot-Carrier-Induced Reliability for Lateral DMOS Transistors With Split-STI Structures

In this work, four kinds of lateral double-diffused MOS (LDMOS) devices with different split shallow trench isolation (STI) structures (Device A: LDMOS with traditional split-STI, Device B: LDMOS with slope-STI, Device C with step-STI and Device D with H-shape-STI) have been fabricated and the hot-carrier reliabilities also have been investigated due to the serious environment they are endured. The maximum bulk current (Ibmax) stress and the maximum gate voltage (Vgmax) stress have been carried out and the inner mechanism of device degradation have been investigated successfully. With the assistance of the T-CAD simulation tools, it is found that the main damage point locates at the STI conners with a mount of interface states generation, inducing serious degradation for these four devices. The Device D owns high hot-carrier reliability due to its special structure with narrow split-STI. The worst device is Device C because of the presence of extra STI damage point. Finally, a mechanism verification, the charge pumping (CP) method has been applied to better understand this work.

Development of a Physical-Topological Model for the Response of a High-Power Vertical DMOS Transistor to the Effect of Pulsed Gamma-Radiation

A method for developing models of semiconductor devices with two-dimensional nonuniform concentration profiles of donors and acceptors in working regions of a semiconductor device structure is for the first time proposed based on a complex of physical-topological modeling of charge carrier transport and process simulation of the forming processes of the device structure. The application of process simulation is due to the need to correctly define the parameters of the semiconductor device structure, which are used as initial data to calculate the electron transport according to the physical-topological model. The parameters of production processes of ion implantation, diffusion, and lithography, which were refined during process simulation, are determined for a high-power metal—oxide—semiconductor (MOS) transistor forming by the double diffusion method in accordance with known electrical characteristics and measured geometrical sizes of the structure. This results in two-dimensional distribution profiles of donors and acceptors in p–n junctions necessary to calculate the transistor breakdown under the effect of pulsed γ radiation. Breakdown processes are modeled with the help of the physical-topological model based on the Poisson and continuity equations as well as expressions for the diffusion and drift current densities in the transistor. Accounting for carriers formed at the instant of γ irradiation is implemented by the introduction of the dependence of the generation coefficient of electron–hole pairs on the radiation-dose power. The results of calculations correlate well with the experimental data, which makes it possible to give a conclusion regarding the adequacy of the proposed complex model.

A Review on Hot-Carrier-Induced Degradation of Lateral DMOS Transistor

With the scaling of process node and increase of operation voltage, the electrical fields and impact ionization generation rates in lateral double-diffused MOS (LDMOS) transistors are obviously increased. As a result, a detailed characterization and understanding for long-term hot-carrier-induced (HCI) effect of LDMOS have been becoming more and more important. This review compares and summarizes the HCI damage locations and degradation mechanisms for all kinds of typical LDMOS devices under different stress conditions. Finally, generalized conclusions on HCI effect of LDMOS are deduced, and some special degradation influence factors brought by the device design technologies are also clarified.

A compact dosimetric system for MOSFETs based on passive NFC tag and smartphone

In this work we describe and evaluate a dosimetric system based on an NFC (Near Field Communication) tag and a smartphone that uses commercial MOSFETs as radiation sensors. The tag is designed with commercial integrated circuits and the smartphone is the power source of the tag configured as a readout unit, user interface and storage unit. The NFC tag is supplied wirelessly by the smartphone via NFC, using a home-made structure to align the tag coil and smartphone coil in order to achieve a good inductive coupling. In this case, the commercial DMOS transistor ZVP3306 is used as dosimeter in unbiased mode, connected to the tag before and after each irradiation session to perform the sensor reading. An evaluation of the dosimetric system has been carried out irradiating three transistors with photon beam of 6MV up to 20Gy. The average sensitivity found is (4.75±0.15)mV/Gy, which is in good agreement with the results found with our previously developed dosimetric system. Therefore, this miniaturised dosimetric system can be considered as a promising and low cost electronic architecture to be used for dosimetry control in radio-therapy treatments.

Hot-Carrier-Induced Degradations and Optimizations for Lateral DMOS Transistor With Multiple Floating Poly-Gate Field Plates

The electrical parameters degradations of lateral double-diffused MOS with multiple floating poly-gate field plates under different stress conditions have been investigated experimentally. For the maximum substrate current ( ${I}_{{\text {submax}}})$ stress, the increased interface states at the bird’s beak mainly result in an on-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}})$ increase at the beginning of the stress, while hot holes injection and trapping into the oxide beneath the edge of real poly-gate turns out to be the dominating degradation mechanism after around 800-s stress, making the ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ decrease. For the maximum operating gate voltage ( ${V}_{{\text {gmax}}})$ stress, the trapped hot electrons in the channel region bring an increase in threshold voltage ( ${V}_{{\text {th}}})$ and ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ , while the generation of large numbers of interface states at the bird’s beak further dramatically increases the ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ . A novel device structurewith a poly-gate partly recessed into the field oxide has been presented to decrease the hot-carrier-induced degradations.

A 60 V Auto-Zero and Chopper Operational Amplifier With 800 kHz Interleaved Clocks and Input Bias Current Trimming

An auto-zero and chopper operational amplifier with a 4.5–60 V supply voltage range is realized, using a $\hbox{0.18}~\mu\hbox{m}$ CMOS process augmented by 5 V CMOS and 60 V DMOS transistors. It achieves a maximum offset voltage drift of 0.02 $~\mu \hbox{V}/^{\circ}\hbox{C}$ , a minimum CMRR of 145 dB, a noise PSD of $\hbox{6.8 nV}/\surd{\rm Hz}$ , and a 3.1 MHz unity gain bandwidth, while dissipating 840 $~\mu\hbox{A}$ of current. Up-modulated chopper ripple is suppressed by auto- zeroing. Furthermore, glitches from the charge injection of the input switches are mitigated by employing six parallel input stages with 800 kHz interleaved clocks. This moves the majority of the glitch energy up to 4.8 MHz, while leaving little energy at 800 kHz. As a result, the requirements on an external low-pass glitch filter is relaxed, and a wider usable signal bandwidth can be obtained. Maximum input bias current due to charge injection mismatch is reduced from 1.5 nA to 150 pA by post production trimming with an on-chip charge mismatch compensation circuit.

Hot-Carrier-Induced On-Resistance Degradation of n-Type Lateral DMOS Transistor With Shallow Trench Isolation for High-Side Application

In this paper, the hot-carrier-induced on-resistance degradation of the n-type lateral DMOS (nLDMOS) transistor with shallow trench isolation (STI) for high-side application has been experimentally investigated. We have found that the dominant on-resistance degradation mechanism of the high-side nLDMOS device (HS-nLDMOS) is the interface state generation at the STI corner. Moreover, the degradation of the on-resistance for high-side application (R on,hs, measured at high drain voltage and high source voltage) is much larger than that for low-side application (R on,ls, measured at low drain voltage and grounded source). This is because the current distribution under the R on,hs state is closer to the damaged STI corner than that under the R on,ls state due to the larger potential difference between the drain and the substrate. Therefore, the on-resistance degradation of the HS-nLDMOS must be measured by using the R on,hs condition, to evaluate the lifetime of the device accurately.

3D Thermal and Mechanical Analysis of a Single Event Burnout

This paper presents a study related to thermal and mechanical behavior of power DMOS transistors during a Single Event Burnout (SEB) process. We use a cylindrical heat generation region for emulating the thermal and mechanical phenomena related to the SEB. In this way, it is avoided the complexity of the mathematical treatment of the ion-device interaction. This work considers locating the heat generation region in positions that are more realistic than the ones used in previous work. For performing the study, we formulate and validate a new 3D model for the transistor that maintains the computational cost at reasonable level. The resulting mathematical models are solved by means of the Finite Element Method. The simulations results show that the failure dynamics is dominated by the mechanical stress in the metal layer. Additionally, the time to failure depends on the heat source position, for a given power and dimension of the generation region. The results suggest that 3D modeling should be considered for a detailed study of thermal and mechanical effects induced by SEBs.

An Easily Implementable Approach to Increase the Energy Capability of DMOS Transistors

DMOS transistors are often subject to high power dissipation and thus substantial self-heating. This limits their safe operating area because very high device temperatures can lead to thermal runaway and subsequent destruction. Because the peak temperature usually occurs only in a small region in the device, it is possible to redistribute part of the dissipated power from the hot region to the cooler device areas. In this way, the peak temperature is reduced, whereas the total power dissipation is still the same. Assuming that a certain temperature must not be exceeded for safe operation, the improved device is now capable of withstanding higher amounts of energy with an unchanged device area. This paper presents two simple methods to redistribute the power dissipation density and thus lower the peak device temperature. The presented methods only require layout changes. They can easily be applied to modern power technologies without the need of process modifications. Both methods are implemented in test structures and investigated by simulations and measurements.

Modeling of the secondary breakdown in a lateral DMOS transistor by irradiation

Using numerical modeling, we have considered the influence of the design-technological parameters of a lateral DMOS-transistor on the resistance to the effect of a secondary breakdown caused by the action of heavy charged particles. Approaches to the optimization of a DMOS-transistor resistant to the action of heavy charged particles are developed. Comparison of the modeling results of the DMOS-transistor’s robustness with the experimental data has been carried out.

Energy capability improvement of power DMOS transistors operating in pulsed conditions

Modern power DMOS transistors greatly benefit from the continuous advances of the technology, which yield devices with very low area-specific RDS,on figures of merit and therefore allow for significantly reduced active areas. However, in many applications, where the devices must dissipate high amounts of energy and thus are subjected to significant self-heating, the active area is not dictated by RDS,on requirements, but by the energy constraints.In this paper, a simple method of improving the energy capability and reliability of power DMOS transistors operating in pulsed conditions is proposed and experimentally verified. The method consists in redistributing the power density from the hotter to the cooler device regions, hence achieving a more homogeneous temperature distribution and a reduced peak temperature. To demonstrate the principle, a simple gate offset circuit is used to redistribute the current density to the cooler DMOS parts. No technology changes are needed for the implementation, only minor changes to the driver circuit are necessary, with a minimal impact on the additional required active area.Improvements in the energy capability from 9.2% up to 39% have been measured. Furthermore, measurements have shown that the method remains effective also if the operating conditions change significantly. The simplicity and the effectiveness of the implementation makes the proposed method suitable to be used in a wide range of applications.

Characterization and modeling of electrical stress degradation in STI-based integrated power devices

Lateral DMOS transistors are widely used in mixed-signal integrated-circuit design as integrated high-voltage switches and drivers. The LDMOS with shallow-trench isolation (STI) is the device of choice to achieve voltage and current capability integrated in the basic CMOS processes. In this review, the electrical characteristics of the STI-based LDMOS transistors are investigated over an extended range of operating conditions through experiments and numerical analysis. The LDMOS high electric-field characteristics are explained to the purpose of investigating the effects on reliability and device performance under hot-carrier stress (HCS) conditions. A review of the HCS modeling is addressed to provide an understanding of the degradation kinetics and mechanisms. TCAD simulations of the degradation are finally proposed to explain the HCS effects on a wide range of biases and temperatures, confirming the experimental results.

A high voltage LDO with dynamic compensation network

A high voltage, low-dropout regulator (LDO) with dynamic compensation network is implemented in Nuvoton 0.6 μm BCD technology. The proposed HVLDO makes use of high voltage tolerance DMOS transistor...

Influence of the On-Chip Metallization on Self-Heating in Integrated Power Technologies

DMOS transistors in integrated power technologies are often subject to significant self-heating and thus high temperatures, which can lead to device failure and reduced lifetime. Hence, it must be ensured that the device temperature does not rise too much. For this, the influence of the on-chip metallization must be taken into account because of the good thermal conductivity and significant thermal capacitance of the metal layers on top of the active DMOS area. In this paper, test structures with different metal layers and vias configurations are presented that can be used to determine the influence of the on-chip metallization on the temperature caused by self-heating. It will be shown how accurate results can be obtained to determine even the influence of small changes in the metallization. The measurement results are discussed and explained, showing how on-chip metallization helps to lower the device temperature. This is further supported by numerical simulations. The obtained insights are valuable for technology optimization, but are also useful for calibration of temperature simulators.

On-Resistance Degradation Induced by Hot-Carrier Injection in SOI SJ-LDMOS

In this brief, anomalous hot-carrier degradation phenomenon in n-type superjunction lateral DMOS transistors on a SOI substrate is investigated. An unexpected on-resistance (Ron) decrease was observed at the beginning of stress, but Ron increases with the stress time. The reason was analyzed with the 3-D simulation of electrical field and impact ionization generation. The injection of hot holes into the field oxide near the drain region leads to the Ron decrease during the early stress period. With the increase of stress time, trapped hot holes accumulated in the field oxide and act as electron defects to trap electrons, altogether with hot electrons trapped in gate oxide above the accumulation region, contributing to Ron increase.