DMOS Transistors Research Articles

Sub-Circuit Based SPICE Model for High Voltage LDMOS Transistors

High voltage lateral DMOS transistors are very difficult to model due to the complex structure. As a result of complexity and the range of variation in transistor structure no general LDMOS model exists. Standard SPICE models of MOSFETs, JFETs together with a resistor have been used in the sub-circuit model. Self-heating effects have been included in a specially design unit. The model shows good overall accuracy.

Self Heating Effects of High Power SOI Vertical DMOS Transistor with Lateral Drain Contacts

Self heating effects in silicon-on-insulator (SOI) high power Vertical Diffused MOS (VDMOS) transistors have been investigated by electro-thermal simulations. Unlike other conventional VDMOS devices, here we work on a modified VDMOS transistor with drain contacts at the surface. In this work we study two different aspects of this transistor namely: (1) Effect of self heating on the device performance and (2) effect of the elevated temperature on the device characteristics. Our simulation results indicate that the temperature distribution is concentrated at the drift region under the gate area and spreads down toward the drain area. The self heating effect gives a notable effect on our newly proposed VDMOS in the on-state (when Vg > Vt), and the breakdown point decreases. As we increase the ambient temperature the breakdown point decreases further.

Input and reverse transfer capacitance measurement of MOS-gated power transistors under high current flow

The measurement principle of the input and reverse transfer capacitance is shown. Function, stability, and operation of the measurement circuits are discussed. The on-state capacitances of a power DMOS transistor were measured under high current conditions of up to 250 A. A strong nonlinear characteristic is observed.

LADISPICE-1.2: a nonplanar-drift lateral DMOS transistor model and its application to power IC TCAD

A circuit simulation program (LADISPICE: LAteral Dmos transistor SPICE) has been developed for simulation and optimisation of power ICs which combine high-power lateral double-diffused MOS transistors with low-voltage logic and control elements on the same chip. This is a development of a previous static model and involves a charge-based dynamic model and a parasitic bipolar junction transistor model. These models have been incorporated into SPICE2G.6 source code and the paper demonstrates the excellent results. This new software represents an effective TCAD tool for the design and simulation of LDMOST power ICs.

Analytical model for dc drain current-voltage relationship in double-diffused channel of DMOS transistor

An analytical model for the dc current-voltage relationship in a double-diffused channel with a lateral nonuniform doping profile of a DMOS transistor has been developed. The equations are similar forms to the current-voltage equations of a conventional MOS transistor. The velocity saturation effect and the mobility reduction effect caused by a perpendicular electric field are also included. The model was verified by comparison with the results of two-dimensional numerical simulation and the fabricated device with a good agreement. The proposed model in this paper can be very useful for designing and analysing power devices with a double-diffused channel structure.

Reliability issues in 650V high voltage bipolar-CMOS-DMOS integrated circuits

Dominant failure modes in high power/high voltage (650V) BCD-technologies are threshold voltage instabilities of the lateral DMOS transistor due to sodium ingression and parasitic leakage currents in low voltage devices induced by high surface potentials originating from the high voltage devices. The failure mechanisms and their temperature dependence have been characterized and process and layout improvements are demonstrated.

Bias temperature reliability of p-channel high-voltage devices

Important shifts in the threshold voltage of high voltage p-channel DMOS transistors have been observed. These shifts are strongly dependent on the stress conditions. An empirical degradation model is derived from measurement data. For a given allowed shift in threshold voltage, this model can determine the safe operating area of the device. The shift in threshold voltage in the p-channel DMOS transistors is explained by excitation and trapping of holes at the oxide-silicon interface at the drain side.

A 70 mΩ intelligent high side switch with full diagnostics

A new, smart power switch for industrial, automotive, and computer applications developed in BCD (Bipolar, CMOS, DMOS) technology is described. It consists of an on-chip 70 m/spl Omega/ power DMOS transistor connected in high side configuration and its driver makes the device virtually indestructible and suitable to drive any kind of load with an output current of 2.5 A. If the load is inductive, an internal voltage clamp allows fast demagnetization down to 55 V below the supply voltage. The device includes novel structures for the driver, the fully integrated charge pump circuit, and its oscillator. These circuits have specifically been designed to reduce electromagnetic interference (EMI) thanks to an accurate control of the output voltage slope and the reduction of the output voltage ripple caused by the charge pump itself. An innovative open load circuit allows the detection of the open load condition with high precision (3 mA /spl plusmn/10% within the temperature range from -25 to 150/spl deg/C and including process spreads). Furthermore, the device protects the load from ground disconnection and is compatible with the new IEC standards concerning burst and surge tests. The quiescent current has also been reduced to 600 /spl mu/A. Diagnostics for CPU feedback is externally available from the chip by two dedicated pins when the following fault conditions occur: open load, overload and short circuit to ground or to the supply voltage, overtemperature, and undervoltage supply.

Experimental evidence of the temperature and angular dependence in SEGR [power MOSFET

The temperature and angular dependence of Single-Event Gate Rupture (SEGR) experiments, conducted on power DMOS transistors, show that a normal incident angle favors SEGR and elevated temperature is insignificant. Both the oxide and substrate response play a major role in determining the SEGR sensitivity.

Modelling and improving the on-resistance of LDMOS RESURF devices

We present in this paper some techniques to decrease the value of the drift region on-resistance of a lateral DMOS transistor (LDMOS). We first evaluate the technique using a shallow implanted layer between the channel and the drain of the transistor, whose doping is somewhat higher than the background doping level. Dose and energy should be carefully calibrated in order to ensure the largest on-resistance improvement but a good trade-off with the breakdown voltage is difficult. Secondly, we assess the on-resistance improvement achievable using a semi-resistive layer deposited between the gate and drain metals above the oxide layer. This will enhance the accumulated drift area and consequently decrease the on-resistance. The achievable improvement is less than for the surface doping technique. We propose to use both techniques to obtain the best on-resistance improvement/breakdown voltage trade-off. Surface doping will be employed to decrease the on-resistance and the semi-resistive layer will keep the breakdown voltage to its optimal value. We assess and demonstrate, with both analytical and numerical analyses, that large improvements can be achieved with these techniques without degrading the voltage handling capacity of the device. The on-resistance can be lowered by 40 to 66%. Experimental LDMOS transistors will be presented which exhibit good agreement with the theoretical predictions.

Forward blocking capability of double gate IGBTs at high temperatures

Forward blocking capability of double gate IGBTs (DG-IGBT) at high temperature was analysed using numerical simulations. It was found that the DG-IGBT behaves like a DMOS transistor at 200°C with much lower leakage current compared with that of a conventional IGBT. This result suggests that the DG-IGBT can safely operate at temperatures up to 200°C.

Theoretical analysis and modeling of submicron channel length DMOS transistors

Previous analytical models of the DMOS transistor are inadequate at the shorter gate lengths, and can lead to spurious predictions of DMOS device behavior. To avoid such shortcomings, an improved DMOS model is proposed to better address DMOS performance issues. These include the identification of desirable device operating regimes and the examination of device frequency response. Increases in DMOS gate capacitance, which have previously been demonstrated only by computer simulation and device measurements, are now modeled analytically. Furthermore, in demonstrating the shortcomings of previous DMOS models, a universal condition for current saturation in MOS devices is derived. The derivation and applicability of the universal condition is independent of mobility model.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High current gain hybrid lateral bipolar operation of DMOS transistors

This paper describes a new operation mode of the DMOS transistor. By utilizing the diffused channel region as base and connecting it to the gate, hybrid lateral bipolar operation is obtained in the device. Current gain higher than 2000 and a cut-off frequency of 1.6 GHz are achieved. Superior breakdown voltages were obtained compared to previously published hybrid devices. It is demonstrated that hybrid operation of a DMOS transistor is a simple way to implement a high gain lateral bipolar transistor, without complex sub-/spl mu/m processing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

TFEL optoelectronic integrated circuit on Si

A unique optoelectronic integrated circuit fabricated with AC thin film electroluminescent (TFEL) devices directly onto the drain of an Si DMOS transistor is demonstrated. DMOS switching controls the high voltage ratio between the TFEL device and DMOS transistor. Active matrix addressing for electroluminescent devices is demonstrated using CMOS circuitry.

A monolithic quad line driver for industrial applications

The device described in this paper is a new quad line driver to be used in the hostile and noisy industrial environment and developed in mixed technology (BCD: Bipolar, CMOS, DMOS). It consists of four independent line drivers, each of which has a rail-to-rail push-pull output stage realized with power DMOS transistors connected in half bridge configuration. Even though the device is designed to be used primarily in the output cards of programmable controllers, it is a general purpose device, since it can drive any kind of load (resistive, capacitive, or inductive) with an output current of 100 mA. The novel structure of the top driver allows full protection of the output stage against any kind of short circuits and/or overloads, providing a linear current limitation. Furthermore, when a channel is tristated, for every applied voltage ranging from ground to the supply voltage, virtually zero current is absorbed from the output. An innovative high efficiency central charge pump circuit has also been designed and implemented, making both a very wide supply voltage operation (6-50 V) and high switching frequency (up to 500 KHz) possible, The device can also be used as a receiver since the input voltage can swing from -10-50 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Impurity profile extraction from semiconductor chips of cellular construction

A novel operation mode is described for the Spreading Resistance Probe (SRP) technique, which permits extraction of impurity profile information from individual device chips. This operation mode, called Array Spreading Resistance Probe (Array SRP), does not require special probing targets on the chip and is restricted to devices of cellular construction. Experimental results are presented for a dynamic MOS memory and for a power DMOS transistor.

A 2-D boundary element method approach to the simulation of DMOS transistors

A boundary element method is introduced for the calculation of two-dimensional potential and electric field distributions in high-voltage DMOS transistors. An algorithm is proposed to determine the dimensions of the depletion layers in two-dimensional geometries. Regions with different permittivities are taken into account using appropriate boundary conditions. As an application, the high-voltage behavior of the DMOS transistors is investigated, and the avalanche breakdown conditions of the transistors are determined by calculating the ionization integral. The results are compared with simulations based on finite difference methods.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modified spice modelling of DC characteristics for high-voltage DMOS transistors

An improved SPICE DC model for high-voltage DMOS transistors is proposed by considering the drift resistance modulation by both the gate and the drain voltages. A nonlinear voltage controlled voltage source (VCVS) is introduced to represent this modulation. Results calculated from this model agree well with the experimental curves of the device DC characteristics.

Simulation and fabrication of submicron channel length DMOS transistors for analog applications

The use of an asymmetric MOS structure for superior analog circuit performance is considered. Results from the fabrication of 1- mu m-gate length DMOS transistors show increases of up to 1.9 in transconductance, 10 in output resistance, and 8 in intrinsic gain when compared to NMOS structures of similar gate length and threshold voltage. Substrate current is also reduced by up to a factor of 10. This represents the first reported results of submicron channel length DMOS transistors. The standard 7 degrees implantation angle has significant impact on DMOS fabrication and is shown to produce a usable asymmetric DMOS from an otherwise symmetric DMOS. An optimal implant energy and diffusion time are shown to exist for DMOS enhancement region formation. Two-dimensional process and device simulators have proved necessary to develop the DMOS process, as well as to qualitatively explain body effect reduction and threshold voltage determination. The DMOS process has successfully yielded experimental circuits including a single ended operational amplifier of folded cascode technology and a 101-state ring oscillator. >

Silicon-on-insulator approach for power IC's integrating vertical DMOS and polycrystalline silicon CMOS thin-film transistors

A novel approach for the monolithic integration of low-voltage logic and analog control circuits with vertical-current flow power transistors is described. This is achieved by fabricating a CMOS device family, using polycrystalline-silicon thin-film transistors (TFTs), on the field oxide of a single-crystal power device. Parasitic interactions between the control and power devices are eliminated in a simple, inexpensive, and easily manufacturable process. The technology is capable of supporting both MOS and bipolar power devices and the presence of the TFT circuits places no restriction on the maximum voltage or current of the power device. The TFTs exhibit good electrical characteristics and the power devices are not compromised by the addition of the TFT control circuits. This concept is demonstrated by the fabrication of a vertical DMOS power transistor with >100-V, >45-A capability, monolithically integrated with current-limiting and temperature-limiting functions. >