Hot-Carrier-Induced Degradations and Optimizations for Lateral DMOS Transistor With Multiple Floating Poly-Gate Field Plates

Abstract

The electrical parameters degradations of lateral double-diffused MOS with multiple floating poly-gate field plates under different stress conditions have been investigated experimentally. For the maximum substrate current ( ${I}_{{\text {submax}}})$ stress, the increased interface states at the bird’s beak mainly result in an on-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}})$ increase at the beginning of the stress, while hot holes injection and trapping into the oxide beneath the edge of real poly-gate turns out to be the dominating degradation mechanism after around 800-s stress, making the ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ decrease. For the maximum operating gate voltage ( ${V}_{{\text {gmax}}})$ stress, the trapped hot electrons in the channel region bring an increase in threshold voltage ( ${V}_{{\text {th}}})$ and ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ , while the generation of large numbers of interface states at the bird’s beak further dramatically increases the ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ . A novel device structurewith a poly-gate partly recessed into the field oxide has been presented to decrease the hot-carrier-induced degradations.