Digital Integrated Circuit Design Research Articles

Recurrent neural network implementation of digital integrated circuits to mitigate challenges in design verification

Design verification is the dominant stage that consumes the most resources in the digital integrated circuit (IC) design process. Design verification is important because human designers imperfectly convert high-level specifications to low-level circuit implementations using standard cell logic, which is nonlinear and complex to predict and characterize. The widening process variations in shrinking process technologies while digital designs grow in scale and complexity to the extent of being impossible to fully or intuitively identify all temporal interactions of a specific design. Deep neural networks (DNN) are being progressively integrated into the sophisticated software tool chain and design process flow of digital IC as artificial intelligence can learn relationships and correlations in complex, high-dimensional, and multi-factorial problems. In this work, we propose to apply DNN to implement digital IC to minimize the complexity of digital design verification. We posit that DNN can learn to implement circuit functions directly from high-level specifications without requiring detailed specifications from the designer. Trained neural networks can be implemented on neuromorphic hardware to achieve greater power and compute efficiencies than the conventional standard cell implementation. We demonstrate that over 150 randomly generated finite state machines (FSM) can be learned effectively with Recurrent Neural Network (RNN) comprising Gated Recurrent Units (GRU) with different complexity as indicated by the number of states and inputs to the FSM. Our proposed methodology of learning RNN GRU implementations of FSM demonstrates a way forward to reduce the cost and effort of design verification, ultimately leading towards faster digital IC design cycles.

Design of High-Speed Area-Efficient VLSI Architecture of 32-Bit Three-Operand Binary Adder

Abstract: Adders are one of the most widely used digital components in digital integrated circuit design. With the advances in technology, the design that offers either high speed, low power consumption, less area, or a combination of them is designed. There are various processes performed by the digital circuits among which arithmetic operations are prominent. Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry save adder (CS3A) is the widely used technique to perform the three-operand addition. However, the ripple carry stage in the CS3A leads to a high propagation delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson (HCA) can also be used for three-operand addition, significantly reducing the critical path delay at the cost of additional hardware. Hence, a new high-speed and area-efficient adder architecture is designed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area, low power, and drastically reduces the adder delay. To design a faster computing system with less hardware we require some other architecture. The proposed architecture will reduce the area as well as the delay by replacing the Han-Carlson adder with the Ladner fisher adder in a Highspeed area-efficient three-operand binary adder. The proposed architecture is synthesized with the zynq-7000 library. The proposed architecture reduces the LUT count and delay by 20 and 0.4 nanoseconds respectively. By using these synthesis results, we noted the performance parameters like the number of LUTs and delay. We compared the adders in terms of LUTs (represents area) and delay value

Optimal Recognition of Volleyball Player’s Arm Movement Track Based on Embedded Microprocessor

An embedded microprocessor is the core part of the integrated circuit system, and it represents one of the highest levels of a digital integrated circuit design. Therefore, the design of low-power embedded microprocessors has become an important research direction in the integrated circuit design. Volleyball has always been a very important sport in our country, and it is a sport that the masses of people like to see. The basic techniques of volleyball include ready posture and movement, serving, hot ball, passing, smashing, and netting. The research content of this article is a simulation study of volleyball players’ arm trajectory optimization recognition. In response to the above problems, this paper proposes an optimized recognition method based on the volleyball player’s arm motion trajectory. The simulation results show that the method has high recognition accuracy and provides a strong scientific basis for improving the volleyball players’ spike skills. Without interference from the right arm, the controller input and position tracking error will not fluctuate in 1 ≤ T ≤ 3 , the controller input is stable, and the output error is zero. Based on the above simulation analysis, it can be seen that the control method does not require the robot kinematics and dynamics model to generate any regression matrix when designing the controller. The controller is suitable for the performance tracking of humanoid robot arms.

Logic Synthesis for Emerging Technologies

Emerging technologies are being considered to replace the conventional CMOS-based design that seems arriving to its end of life due to the limits of MOS transistor shrinking. However, since those novel devices are not necessarily switch-based ones, the traditional AND/OR logic synthesis process in the digital integrated circuit design flow tends to become inefficient, whereas threshold logic paradigm seems to be more appropriate for them. In this context, different methods for threshold logic synthesis, suitable for emerging technologies, are reviewed in this paper. The majority logic based design is also discussed herein since it represents a subset of threshold logic domain, and many new technologies have presented the 3-input majority Boolean function as the most basic logic gate. Experimental data, presented in previous works, are used to illustrate and compare the performance of the state-ofthe-art logic synthesis methods related to

Twenty Years of Near/Sub-Threshold Design Trends and Enablement

This brief surveys the past 20 years of near/sub-threshold digital integrated circuit design. Most of the chips have been highly characterized for voltage scaling down to near/sub-threshold, and a significantly custom design effort has been reported to achieve reliable operation. In this brief, we address the challenges of process variations and discuss the circuits and methods used over the years to minimize this impact. We discuss the advantages of standard-cell library design and provide a more involved pruning method to improve performance and robustness. Finally, we discuss the developments of the usually ignored power delivery techniques for near/sub-threshold circuits. We motivate the use of voltage stacking as a new power delivery technique for near/sub-threshold. This brief provides the basic enablement approaches for designing a chip operating in the near/sub-threshold region based on our experience.

Parallel Combinational Equivalence Checking

Combinational equivalence checking (CEC) has been widely applied to ensure design correctness after logic synthesis and technology-dependent optimization in digital integrated circuit design. CEC runtime is often critical for large designs, even when advanced techniques are employed. Three complementary ways for enabling parallelism in CEC are proposed, addressing different design and verification scenarios. The experimental results have demonstrated the speedups up to $63\times $ when comparing the proposed approach to a single-threaded implementation of a similar CEC engine. A practical impact of such a speedup, for instance, is the runtime reduction from 19 h to only 18 min when checking equivalence of AND-inverter graphs comprising more than 20 million nodes. Therefore, the proposed solution presents great potential for improving current electronic design automation environments.

A digital interface integration circuit design for high precision quartz-gyro

A design of digital application specific integrated circuit (ASIC) of quartz-gyro is proposed in this paper. The digital drive circuit with fast-start oscillation and digital detection circuit with low noise are adopted to implement the digital output of the main circuit node and high precision angular velocity detection. The interface circuit is fabricated in a standard 0.35 [Formula: see text]m CMOS technology and test result shows the angular random walk and zero stability are [Formula: see text]/[Formula: see text] and [Formula: see text]/h ([Formula: see text]), respectively. The bias-instability is [Formula: see text]/h (Allen). The nonlinearity is limited to 0.035% and the zero temperature drift is [Formula: see text]/h from [Formula: see text] to [Formula: see text]. The chip exhibits great superiority on the aspects of high precision angular velocity digital detection and temperature characteristics of overall system.

Computational study of silicene nanoribbon tunnel field-effect transistor

Stable room temperature operation of field-effect transistor (FET) based on two-dimensional silicon (silicene) has recently been reported. Like graphene, silicene is a Dirac cone material. Silicene-based devices provide high off-state leakage current due to lack of a significant bandgap. However, quantum confined silicene nanoribbon (SiNR) shows observable bandgap which can be used for making switching transistors for digital integrated circuit design. Contrary to metal oxide semiconductor FET (MOSFET), tunnel field-effect transistor (TFET) overcomes the physical limit of scaling of supply voltage. In this work, we present structure and characteristics of SiNR TFET using atomistic simulation based on self-consistent solution of 3D Poisson and Schrodinger equations within the non-equilibrium Green’s function formalism. Performances are also compared with the International Technology Roadmap for Semiconductors projected high performance requirements of 2026 nMOSFETs.

Obstacle-Avoiding Open-Net Connector With Precise Shortest Distance Estimation

At the end of digital integrated circuit (IC) design flow, some nets may still be left open due to engineering change order (ECO). Resolving these opens could be quite challenging for some huge nets such as power ground nets because of a large number of obstacles and greatly distributed net components. Existing studies on multilayer obstacle-avoiding rectilinear Steiner trees may not be applicable to solve this problem because they assume the pins of an input net is a set of points, while the discrete net components in this problem can be regarded as a set of rectilinear pins. In this paper, we develop an efficient open-net connector that can deal with rectilinear pins. The proposed algorithm flow minimizes the total connection cost based on precise estimation of the shortest distance between each pair of rectilinear net components with the presence of complex obstacles. The experimental results show that the proposed flow can outperform the top-three teams of 2017 CAD contest at ICCAD and a state-of-the-art work in terms of total connection cost or runtime efficiency.

HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs

To mitigate the excess timing margin in conventional digital integrated circuit design, resilient circuits were proposed. The current techniques however either have a large error-detecting register or have difficulty in wide-voltage-range (down to near-threshold) operation. In this paper, we propose a light-weight holosymmetrical transition detector (HTD) that can work reliably at near-threshold to normal VDD with fast response time. Combined with a conventional latch, the HTD-latch is used to replace the end point flip-flop for timing error prediction with an area overhead of only 9.5% over a conventional flip-flop. Besides, we optimize the speculation window and design an adaptive duty-cycle control mechanism to reduce the short-path padding overhead in a resilient circuit. In addition, with voltage scaling, we keep the system working at the point before the first failure by using local detection and global clock gating, which needs neither architectural circuit change nor complicated error recovery mechanism. We apply the above-mentioned three techniques on an eighth-order filter test chip in a 40-nm CMOS process. The measurement results demonstrate that the proposed HTD can work robustly at 0.474–1.1 V. With 4.37% area overhead in total, the proposed resilient technique improves performance by 179.31%/28.2% and energy efficiency by 45.6%/28.1% in a near- $V_{\mathrm {TH}}$ (0.474 V)/super- $V_{\mathrm {TH}}$ (1.1 V) operation, as compared with the baseline design. Therefore, our proposed HTD-based resilient technique can improve the energy efficiency of circuits by almost eliminating all the timing margins.

Digital Logic Synthesis for 470 Celsius Silicon Carbide Electronics

Abstract Advancements in Silicon Carbide (SiC) digital integrated circuit (IC) design have enabled the ability to design complex, dense, digital blocks. Because of the large number of transistors, these complex digital designs make the time and risk of hand-crafted digital design, which has been the norm for SiC, too costly and risky. For large scale integrated digital circuits, computer aided design (CAD) tools are necessary, specifically the use of automatic synthesis, rule-based placement and signal routing software. The tools are used in progression as a design flow and are necessary for the timely and accurate creation of high-density digital designs. Application of an automated digital design flow to high-temperature SiC processes presents new challenges, such as extraction of timing characteristics at high temperatures, specifically above 400°C, as well as managing the complexity of synthesis, optimization of cell placement, verification of timing enclosure, and identifying routing constraints. These activities all require a willingness to extend and enhance the CAD software. Presented is a high temperature SiC digital synthesis flow. This flow is fully integrated with the characterization of a standard cell library that considers the variation of voltage, temperature, and process characteristics. A digital controller for a 10,000-pixel UV focal plan array (FPA) in a SiC CMOS process was designed using this high temperature digital flow. The controller is comprised of a finite state machine (FSM), that monitors several counters, shift registers and combinational logic feedback signals. The FSM is configured to optimize the FPA for different applications and exposures. The Register-Transfer Level (RTL) design of the FSM produces between 900 and 1,000 gates, depending on the temperature-dependent time closure with a total footprint of 14mm2. Typical SiC processes present a non-monotonic clock speed over temperature. The advantage of this digital design flow is that it allows the designer to target a temperature corner for the netlist design but verify its operation over a > 400°C operating range. This flow is currently being enhanced for use with NASA's SiC JFET-R process to create a high temperature communication protocol interface.

Analysis of power consumption and delay of an inverter circuit using TMJLSRG MOSFET for the design of digital integrated circuit

Analysis of power consumption and delay of an inverter circuit using TMJLSRG MOSFET for the design of digital integrated circuit

Analysis of power consumption and delay of an inverter circuit using TMJLSRG MOSFET for the design of digital integrated circuit

This paper represents delay and power analysis of an inverter using a triple-material junctionless surrounding gate MOSFET (TMJLSRG) to design integrated circuit. TCAD tools have been used for the purpose of simulation. The delay and power consumption are the vital design metrics to design the circuit in nano level. In this work, the variation of power consumption has been reported for different values of power supply voltage VDD and channel length. Delay is also reported with respect to VDD .Moreover, power consumption has been reported for the gate engineered device for different ratio of gate length. The results are satisfactory to design low power and high speed digital integrated circuit using TMJLSRG MOSFET.

Scalable [formula omitted]-power law based MOSFET model for characterization of ultra deep submicron digital integrated circuit design

Analytical circuit design, optimization, characterization and development of design methodology for digital circuits using nanoscale CMOS devices require compact equations. Such equations need to include first order short channel phenomena relevant to the nanoscale technology nodes being used. The present paper demonstrates that α-power model can be updated to include velocity overshoot necessary to characterize devices at ultradeep submicron technology nodes. Further, the three α-power model parameters (velocity saturation index α, transconductance parameter K1 and threshold voltage Vth) expressing MOSFET drain current has been expressed in terms of predictive technology model (PTM) parameters. Representative basic CMOS cells belonging both to inverter and transmission gate categories have been analytically characterized using the updated α-power model up to ultradeep submicron technology node with BSIM verification. It has been shown that consideration of velocity overshoot is important for accurate prediction below 40nm.

FPGA-based elastic in-circuit debugging for complex digital logic design

In digital integrated circuit design, the emergence of intellectual property (IP) reuse technology reduces the complexity of system on chip (SoC) design, and makes the SoC have more and more powerful functions. Unfortunately, it also increases the verification difficulty, and extends the whole system design cycle. Aiming at the low efficiency of stimulating mechanism, the difficulty of real-time signal monitoring and non-reusability of module-level verification platform for IP design based on field-programmable gate array (FPGA), we propose a kind of elastic in-circuit debugging method for complex digital logic design so as to optimise the verification process. Based on the extension of traditional IP verification platform, we build the IP in-circuit debugging platform, which has some advantages such as elasticity, configurability, extensibility and humanisation. After verification of multiple IP instances, the results show that the method has strong universality and can improve the efficiency of IP verification.

Hardware Security of CE Devices [Hardware Matters

In my previous columns, I have covered various topics, including the evolution of the intellectual property core industry, digital integrated circuit (IC) design flow, high-level perspectives on intellectual property (IP) cores, and the transient fault resiliency of IP cores. Though one of my previous columns focused on providing a generic cognizance about the protection of reusable IP cores, it did not delve deep into the threat models and defense mechanisms against hardware trojans and IP piracy. This column discusses hardware security of consumer electronics (CE) devices, focusing primarily on threat models and defense mechanisms against two major attacks: hardware trojans and IP piracy.

EMC Qualification Methodology for Semicustom Digital Integrated Circuit Design

In this paper, a simulation methodology and an electromagnetic compatibility qualification environment (EQE) are developed to verify the electromagnetic susceptibility of semicustom digital integrated circuits (IC) during the design phase. The immunity levels of the digital circuits are estimated by the functional failure and delay change caused by the external noise which is injected by bulk current injection (BCI) and direct power injection (DPI) methods. The model for the device under test (DUT), the standard cell parasitic model, and the equivalent circuit model of BCI and DPI test setup are developed for the IC immunity test. All test components and on-chip circuit models are linked by EQE to analyze the target DUT. The EQE can be applied to predict the immunity level of the design at the schematic level and postlayout level design. To validate the accuracy of the proposed simulation tool, EQE is applied to the design process of a clock divider (CKD) and a serial peripheral interface (SPI) circuits to verify their immunity levels. The CKD and SPI circuits are designed and fabricated using Magna 180 nm Complementary metal-oxide semiconductor (CMOS) technology. The immunity levels generated by the EQE are compared with the experimental measurement results. The comparison shows good agreement between simulation and measurement.

Silicene Nanoribbon Tunnel Field Effect Transistor

Stable room temperature operation of field effect transistor (FET) based on two-dimensional silicon (silicene) has recently been reported. Like graphene, silicene is a Dirac cone material. Silicene-based devices provide high off-state leakage current due to lack of a significant bandgap. However, quantum confined silicene nanoribbon (SiNR) shows observable bandgap which can be used for making switching transistors for digital integrated circuit design. Contrary to metal oxide semiconductor FET (MOSFET), tunnel field effect transistor (TFET) overcomes the physical limit of scaling of supply voltage. In this work, we present structure and characteristics of SiNR TFET using atomistic simulation based on self-consistent solution of 3D Poisson and Schrödinger equations within the non-equilibrium Green’s function (NEGF) formalism. Performances are also compared with the International Technology Roadmap for Semiconductors (ITRS) projected high performance requirements of 2026 nMOSFETs.

Complex High-Temperature CMOS Silicon Carbide Digital Circuit Designs

The need for dependable digital circuitry with the capability to operate reliably in high-temperature environments has been increasing drastically in applications such as automobile, aerospace, oil exploration, and power electronics. However, wide temperature swings significantly alter the threshold voltage of individual transistors, which adversely affects circuit timing in traditional synchronous designs. Such timing changes may in turn violates the setup and hold times of the clocked components, leading to potential circuit failure. This paper presents a complex digital integrated circuit design methodology using both synchronous and asynchronous logic for comparison in a young silicon carbide (SiC) design process developed by Raytheon UK. Seventeen circuits were designed, fabricated, and tested with results showing correct operation at temperatures at and above the target temperature of 300 °C.

Variation-aware clock network buffer sizing using robust multi-objective optimization

Many engineering optimization problems include unavoidable uncertainties in parameters or variables. Ignoring such uncertainties when solving the optimization problems may lead to inferior solutions that may even violate problem constraints. Another challenge in most engineering optimization problems is having different conflicting objectives that cannot be minimized simultaneously. Finding a balanced trade-off between these objectives is a complex and time-consuming task. In this paper, an optimization framework is proposed to address both of these challenges. First, we exploit a self-calibrating multi-objective framework to achieve a balanced trade-off between the conflicting objectives. Then, we develop the robust counterpart of the uncertainty-aware self-calibrating multi-objective optimization framework. The significance of this framework is that it does not need any manual tuning by the designer. We also develop a mathematical demonstration of the objective scale invariance property of the proposed framework. The engineering problem considered in this paper to illustrate the effectiveness of the proposed framework is a popular sizing problem in digital integrated circuit design. However, the proposed framework can be applied to any uncertain multi-objective optimization problem that can be formulated in the geometric programming format. We propose to consider variations in the sizes of circuit elements during the optimization process by employing ellipsoidal uncertainty model. For validation, several industrial clock networks are sized by the proposed framework. The results show a significant reduction in one objective (power, on average 38 %) as well as significant increase in the robustness of solutions to the variations. This is achieved with no significant degradation in the other objective (timing metrics of the circuit) or reduction in its standard deviation which demonstrates a more robust solution.