FPGA-based elastic in-circuit debugging for complex digital logic design

Abstract

In digital integrated circuit design, the emergence of intellectual property (IP) reuse technology reduces the complexity of system on chip (SoC) design, and makes the SoC have more and more powerful functions. Unfortunately, it also increases the verification difficulty, and extends the whole system design cycle. Aiming at the low efficiency of stimulating mechanism, the difficulty of real-time signal monitoring and non-reusability of module-level verification platform for IP design based on field-programmable gate array (FPGA), we propose a kind of elastic in-circuit debugging method for complex digital logic design so as to optimise the verification process. Based on the extension of traditional IP verification platform, we build the IP in-circuit debugging platform, which has some advantages such as elasticity, configurability, extensibility and humanisation. After verification of multiple IP instances, the results show that the method has strong universality and can improve the efficiency of IP verification.