A New Authentication Scheme for the Protection of FPGA Based IP Designs

Abstract

Intellectual Property (IP) plays an essential part in the design-for-reuse technique which minimizes cost and development time of System-on-Chip (SoC) designs. But, sharing IP designs has many security risks and moreover, traditional methods for IP protection are time consuming and are often unaffordable and thus, protection of IP designs in VLSI have become an active research area. Field Programmable Gate Array (FPGA) uses bitstream encryption method to protect Intellectual Property (IP) cores once it is loaded onto the FPGA. Static Random Access Memory ( SRAM) based FPGA are volatile and the requirement of configuring on each power up results in attacks such as cloning, reverse engineering or tampering of the bitstream. So, advanced and novel techniques beyond bitstream encryption are necessary to ensure FPGA design security. This research work focuses on establishing an effective method for embedding IP designer information starting from synthesis tool level. High security is also provided to IP cores by using a novel hardware in the FPGA called Secure Start Hardware (SSH). A minimal cryptographic protocol is introduced to achieve an authenticated channel between the system designer (SD) and Secure Start Hardware (SSH). The proposed approach and design is tested and it is observed to provide efficient results.