Abstract
The design of fault tolerant systems for space applications mandates the use of new techniques to construct robust and reliable systems. Nowadays modern Field Programmable Gate Arrays (FPGA) provide very high logic capacity and low power consumption profiles. The size, weight and thermal characteristics are acceptable even for the non-space grade category. A major trend is to use the commercial grade FPGAs to build satellite systems using fault tolerant design techniques. The commercial grade components are often state-ofart and provide faster and better performance than the well tested and approved space components. In low cost satellite missions, it is acceptable to bear some risk in return for using the widely accessible and low cost commercial grade components. In this paper we present the ongoing development of a robust embedded computer system to be used as the main on-board computer of Micro and Nano satellites at Kyushu Institute of Technology, Japan. The system makes use of the soft IP cores available for the Microblaze processors from Xilinx Inc. The Xilinx FPGAs are Static Random Access Memory (SRAM) based and do not apply the anti-fused technology. They need periodic scrubbing for the SRAM memory holding the hardware design. Xilinx introduced a reconfigurable technique to facilitate the reconfiguration of their FPGAs even while operating without affecting other parts of the design. This technique is known as partial reconfiguration, in which parts of the system will be reconfigured while the rest of the system is functioning without interruption. It provides a facility to improve the development of fault tolerant FPGA designs through read-back and then reconfiguration of faulty FPGA modules. We present our use of this technique to build a robust On-Board computer system on SRAM based FPGAs using soft Intellectual Property (IP) cores. The results of applying this technique are discussed in terms of gains, drawbacks and the effects on the overall fault tolerance performance.
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