Design of High-Speed Area-Efficient VLSI Architecture of 32-Bit Three-Operand Binary Adder

Abstract

Abstract: Adders are one of the most widely used digital components in digital integrated circuit design. With the advances in technology, the design that offers either high speed, low power consumption, less area, or a combination of them is designed. There are various processes performed by the digital circuits among which arithmetic operations are prominent. Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry save adder (CS3A) is the widely used technique to perform the three-operand addition. However, the ripple carry stage in the CS3A leads to a high propagation delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson (HCA) can also be used for three-operand addition, significantly reducing the critical path delay at the cost of additional hardware. Hence, a new high-speed and area-efficient adder architecture is designed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area, low power, and drastically reduces the adder delay. To design a faster computing system with less hardware we require some other architecture. The proposed architecture will reduce the area as well as the delay by replacing the Han-Carlson adder with the Ladner fisher adder in a Highspeed area-efficient three-operand binary adder. The proposed architecture is synthesized with the zynq-7000 library. The proposed architecture reduces the LUT count and delay by 20 and 0.4 nanoseconds respectively. By using these synthesis results, we noted the performance parameters like the number of LUTs and delay. We compared the adders in terms of LUTs (represents area) and delay value