Digital Integrated Circuit Design Research Articles

Variation-aware clock network buffer sizing using robust multi-objective optimization

Many engineering optimization problems include unavoidable uncertainties in parameters or variables. Ignoring such uncertainties when solving the optimization problems may lead to inferior solutions that may even violate problem constraints. Another challenge in most engineering optimization problems is having different conflicting objectives that cannot be minimized simultaneously. Finding a balanced trade-off between these objectives is a complex and time-consuming task. In this paper, an optimization framework is proposed to address both of these challenges. First, we exploit a self-calibrating multi-objective framework to achieve a balanced trade-off between the conflicting objectives. Then, we develop the robust counterpart of the uncertainty-aware self-calibrating multi-objective optimization framework. The significance of this framework is that it does not need any manual tuning by the designer. We also develop a mathematical demonstration of the objective scale invariance property of the proposed framework. The engineering problem considered in this paper to illustrate the effectiveness of the proposed framework is a popular sizing problem in digital integrated circuit design. However, the proposed framework can be applied to any uncertain multi-objective optimization problem that can be formulated in the geometric programming format. We propose to consider variations in the sizes of circuit elements during the optimization process by employing ellipsoidal uncertainty model. For validation, several industrial clock networks are sized by the proposed framework. The results show a significant reduction in one objective (power, on average 38 %) as well as significant increase in the robustness of solutions to the variations. This is achieved with no significant degradation in the other objective (timing metrics of the circuit) or reduction in its standard deviation which demonstrates a more robust solution.

Low-Power FIR Filter Design Using Hybrid Artificial Bee Colony Algorithm with Experimental Validation Over FPGA

Assessment of power consumption is very important for an efficient digital integrated circuit design. Dynamic power in digital programmable CMOS-based processors depends on the switching activity. Specifically in its subcomponents like FIR filter, power consumption can be directly related to the node switching activity. Minimization of power consumption can be done by reducing the transitions or dissimilarities in filter coefficients. Evolutionary algorithms (EAs) have been found to be very effective for optimized FIR filter design because of nonlinear, nondifferentiable, multimodal and nonconvex nature of the associated optimization problem. However, all the existing evolutionary optimization-based design techniques aim at meeting the frequency domain specifications without concentrating on minimizing power consumption. In the present work, a novel EA, i.e., hybrid artificial bee colony algorithm, has been proposed and further applied for FIR filter design. The filter design task aims at satisfying the dual objectives of meeting the desired frequency domain specifications and power minimization.

VLSI Design with Alliance Free CAD Tools: an Implementation Example

This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding.

Case-Based Instruction in Digital Integrated Circuit Design Courses for Non-Major Students

In this paper, a preliminary study using case-based teaching methodology in a digital IC design course is described. The proposed case-based course consists of ten lecture topics with hands-on labs and two projects. Each topic covers a design case example which contains illustrations of physical structure, hardware description language (HDL) codes, truth tables, waveform, and comments. Students can comprehend the essence of HDL by referring to physical logic gates, truth table, and waveform with HDL codes. This helps students to understand the abstract nature of HDL-based design flow especially for non-EE major undergraduates. To illustrate the effect of case-based teaching methodology instruction for non-major undergraduates, a specific class was constructed by 56% major and 44% non-major undergraduates. At the end of the course, both major and non-major undergraduates verified all labs and projects successfully. The questionnaire statistics show that most of the students like the course with case-based guidance. They all look forward to taking other similar engineering courses in the future.

Design of High Performance Carry Select Adder

Adders are one of the widely used digital components in digital integrated circuit design. Addition is the basic operation used in almost all computational systems. Therefore, the efficient implementation and design of arithmetic units requires the binary adder structures to be implemented in an equally efficient manner. A ripple carry adder has smaller area but less speed. A carry look-ahead adder is faster though its area requirements are high. Carry select adders (CSLA) lie in middle. In this work a novel carry select adder using Binary Excess Converter (BEC) is proposed. It provides good compromise between cost and performance thereby establishing a proper trade-off between time and area complexities. In this work Tanner EDA is used for the comparison of all adders – Ripple carry adder, Bitwise carry select adder, Square root carry select adder, proposed carry select adder using BEC.

Toward Printed Integrated Circuits based on Unipolar or Ambipolar Polymer Semiconductors

For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (μ) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of μ ∼ 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge transport properties. Among this class of materials, various polymers can show well balanced electrons and holes mobility, therefore being indicated as ambipolar semiconductors, good environmental stability, and a small band-gap, which simplifies the tuning of charge injection. This opened up the possibility of taking advantage of the superior performances offered by complementary "CMOS-like" logic for the design of digital ICs, easing the scaling down of critical geometrical features, and achieving higher complexity from robust single gates (e.g., inverters) and test circuits (e.g., ring oscillators) to more complete circuits. Here, we review the recent progress in the development of printed ICs based on polymeric semiconductors suitable for large-volume micro- and nano-electronics applications. Particular attention is paid to the strategies proposed in the literature to design and synthesize high mobility polymers and to develop suitable printing tools and techniques to allow for improved patterning capability required for the down-scaling of devices in order to achieve the operation frequencies needed for applications, such as flexible radio-frequency identification (RFID) tags, near-field communication (NFC) devices, ambient electronics, and portable flexible displays.

Area-efficient reconfigurable-array-based oscillator for standard cell characterisation

Today's multi-million digital integrated circuit design highly depends on the quality of the standard cell library. In this study, an all-digital reconfigurable-array-based test structure is presented to test the quality (i.e. functionality and performance) of all types of logic gates in the standard cell library using the reconfigurable array of gate delay measurement cell. The gate delay is estimated using the least squares method with measured reconfigurable ring oscillator's (RO) period/frequency. As the least squares method averages out the random noise in the measured RO period, measured gate delay is estimated accurately. The reconfigurable-array structure can easily isolate a faulty standard cell from a non-faulty standard cell. The test structure is area efficient with a saving of 1.6× and 2× area compared with the normal RO-based delay measurement in 180 nm and 65 nm technology node, respectively. A subset of standard cells is tested using this reconfigurable-array structure. A test chip has been fabricated in an industrial 180 nm technology node to study the feasibility of the approach. The measured results from 20 chips are reported to show the amount of within-die and die-to-die variation.

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment

With the growing size of modern designs and more strict time-to-market constraints, design errors can unavoidably escape pre-silicon verification and reside in silicon prototypes. Due to those errors and faults in the fabrication process, silicon debug has become a necessary step in the digital integrated circuit design flow. Embedded hardware blocks, such as scan chains and trace buffers, provide a means to acquire data of internal signals in real time for debugging. However, the amount of the data is limited compared to pre-silicon debugging. This paper presents an automated software solution to analyze this sparse data to detect suspects of the failure in both the spatial and temporal domain. It also introduces a technique to automate the configuration process for trace-buffer-based hardware in order to acquire helpful information for debugging the failure. The technique takes the hardware constraints into account and identifies alternatives for signals not part of the traceable set so that their values can be restored by implications. The experiments demonstrate the effectiveness of the proposed software solution in terms of run-time and resolution.

Undergraduate Curriculum Development for Digital Integrated Circuit Design

This article describes the development of a Digital Integrated Circuit Design curriculum, which includes how to select the design level and how to implement the design. The curriculum is for the undergraduates in grade four, whose major is microelectronics. The development is in the background of very large scale integrated circuits. Since the popular design flow is a hierarchy of abstraction levels, the goal of the curriculum is to develop the students’ ability to design an actual circuit from scratch. Comparison is provided from two aspects. The first aspect is the contents of various published textbooks. The second aspect is the contents of similar courses in famous universities.

Three-dimensional multi-terminal superconductive integrated circuit inductanceextraction

Accurate inductance calculations are critical for the design of both digital and analoguesuperconductive integrated circuits, and three-dimensional calculations are gainingimportance with the advent of inductive biasing, inductive coupling and sky plane shieldingfor RSFQ cells. InductEx, an extraction programme based on the three-dimensionalcalculation software FastHenry, was proposed earlier. InductEx uses segmentationtechniques designed to accurately model the geometries of superconductive integratedcircuit structures. Inductance extraction for complex multi-terminal three-dimensionalstructures from current distributions calculated by FastHenry is discussed. Results forboth a reflection plane modelling an infinite ground plane and a finite segmentedground plane that allows inductive elements to extend over holes in the groundplane are shown. Several SQUIDs were designed for and fabricated with IPHT’s1 kA cm − 2 RSFQ1D niobium process. These SQUIDs implement a number of loop structures thatspan different layers, include vias, inductively coupled control lines and ground planeholes. We measured the loop inductance of these SQUIDs and show how theresults are used to calibrate the layer parameters in InductEx and verify theextraction accuracy. We also show that, with proper modelling, FastHenry canbe fast enough to be used for the extraction of typical RSFQ cell inductances.

Application of genetic algorithm in computing the tradeoffs between power consumption versus delay in digital integrated circuit design

This paper presents a novel methodology to obtain the entire power consumption versus delay tradeoff curve for the critical paths of a combinational logic circuit in a very efficient way using the genetic algorithm (GA). In order to evaluate the proposed algorithm the most representative set of two-level and multi-level networks from the MCNC91 benchmark suite were processed. The required computational effort, measured in terms of CPU time, is several times better for the proposed GA optimization technique than liner programming (LP) technique. On the other hand, the optimal design points obtained by the GA and LP techniques are very close to each other to within 0.3%.

Digital integrated circuit design: from VLSI architectures to CMOS fabrication

VLSI circuits are ubiquitous in the modern world, and designing them efficiently is becoming increasingly challenging with the development of ever smaller chips. This practically oriented textbook covers the important aspects of VLSI design using a top-down approach, reflecting the way digital circuits are actually designed. Using practical hints and tips, case studies and checklists, this comprehensive guide to how and when to design VLSI circuits, covers the advances, challenges and past mistakes in design, acting as an introduction to graduate students and a reference for practising electronic engineers.

Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach

A highly collision-resistive RFID system multiplexes communications between thousands of transponders and a single reader using TH-CDMA based anti-collision scheme. This paper focuses on the back-end design consideration of such an RFID system with the deployment of high-level modeling techniques, accompanying a technical comparison of physical-level description, hardware-based emulation, and software-based simulation. A new rapid-prototyping simulation system was constructed to evaluate the robustness of a multiplexed RFID link system with more than 1,000 channels in the presence of field disturbances, and the design parameters of the back-end digital signal processing that dominated anti-collision performance were explored. Finally, the derived optimum parameters were applied to the design of a back-end digital integrated circuit to be installed in collision-resistive transponder circuitry.

Ultra-low-power design

In this article, we describe how such an integrated approach has indeed made it possible to produce a PicoNode that meets the original goals. The resulting node combines innovative technologies, such as radio-frequency microelectromechanical systems (RF-MEMS) with ultra-low-power RF and digital integrated circuit (IC) design, and employs aggressive energy-scavenging and packaging techniques. For these technological advances to come to their full fruition, they must be complemented by novel opportunistic networking and wireless protocol schemes that virtually eliminate standby power while still providing robustness

Communication Scheme for a Highly Collision-Resistive RFID System

A highly collision-resistive RFID system multiplexes communications between thousands of tags and a single reader in combination with time-domain multiplexing code division multiple access (TD-CDMA), CRC error detection, and re-transmission for error recovery. The collision probability due to a random selection of CDMA codes and TDMA channels bounds the number of IDs successfully transmitted to a reader during a limited time frame. However, theoretical analysis showed that the re-transmission greatly reduced the collision probability and that an ID error rate of 2.5 × 10-9 could be achieved when 1,000 ID tags responded within a time frame of 400 msec in ideal communication channels. The proposed collision-resistive communication scheme for a thousand multiplexed channels was modeled on a discrete-time digital expression and an FPGA-based emulator was built to evaluate a practical ID error rate under the presence of background noise in communication channels. To achieve simple anti-noise communication in a multiple-response RFID system, as well as unurged re-transmission of ID data, adjusting of correlator thresholds provides a significant improvement to the error rate. Thus, the proposed scheme does not require a reader to request ID transmission to erroneously responding tags. A reader also can lower noise influence by using correlator thresholds, since the scheme multiplexes IDs by CDMA-based communication. The effectiveness of the re-transmission was confirmed experimentally even in noisy channels, and the ID error rate derived from the emulation was 1.9 × 10-5. The emulation was useful for deriving an optimum set of RFID system parameters to be used in the design of mixed analog and digital integrated circuits for RFID communication.

Teaching Mixed-Signal Integrated Circuit Design to Undergraduates

A two-course sequence that teaches the basic concepts associated with digital, analog, and mixed-signal integrated circuit design for senior-level undergraduate students has been developed. The use of hands-on experiences using custom integrated circuits is employed to help teach these complex topics. This sequence has been taught for three years, and the affective learning has been assessed through precourse and postcourse surveys, focus groups, and in-class surveys.

ASIC by Design - Automated design of digital signal processing application-specific integrated circuits

Comparing the optimized results to the baseline, we are achieving typically 10-20/spl times/ improvement in PDA. This allows gap closure to approach the optimization of a full custom design process while preserving the automation and design efficiency of ASIC design. Additionally, the reuse of each macro saves two to three staff-months, and each optimization script saves one to two staff-months. Hence, we achieve an overall reduction in design time even though it takes extra time to run these optimization tools. The mission-specific processing (MSP) design flow can be applied to a wide range of DSP and other digital processing applications, where high performance and integration is required. The macros developed were selected to span important algorithms commonly performed in communication, radar, navigation, targeting, electronic warfare and other military and national security applications.

Low power, high speed, charge recycling CMOS threshold logic gate

A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.

Novel extension of neu-MOS techniques to neu-GaAs

The neuron-MOS (neu-MOS) transistor, recently discovered by Shibata and Ohmi in 1991 [T. Shibata, T. Ohmi, International Electron Devices Meeting, Technical Digest, 1991] uses capacitively coupled inputs onto a floating gate. Neu-MOS enables the design of conventional analog and digital integrated circuits with a significant reduction in transistor count [L.S.Y. Wong, C.Y. Kwok, G.A. Rigby, in: Proceedings of the 1997 IEEE Custom Integrated Circuits Conference, 1997; B. Gonzales, D. Abbott, S.F. Al-Sarawi, A. Hernandez, J. Garcia, J. López, in: Proceedings of the XIII Design of Circuits and Integrated Systems Conference (DCIS'98), 1998, pp. 62–66]. Furthermore, neu-MOS circuit characteristics are relatively insensitive to transistor parameter variations inherent in all MOS fabrication processes. Neu-MOS circuit characteristics depend primarily on the floating gate coupling capacitor ratios. It is also thought that this enhancement in the functionality of the transistor, i.e. at the most elemental level in circuits, introduces a degree of flexibility that may lead to the realisation of intelligent functions at a system level [T. Ohmi, T. Shibata, in: Proceedings of the 20th International Conference on Microelectronics, vol. 1, 1995, pp. 11–18]. This paper extends the neu-MOS paradigm to complementary gallium arsenide based on HIGFET transistors. The design and HSPICE simulation results of a neu-GaAs ripple carry adder are presented, demonstrating the potential for very significant transistor count and area reduction through the use of neu-GaAs in VLSI design. Preliminary simulations indicate a reduction of a factor of four in transistor count for the same power dissipation as conventional complementary GaAs. The small gate leakage is shown to be useful in eliminating unwanted charge build-up on the floating gate.

Digital integrated circuit design

Preface 1. THE BASICS 1.1 Simple NMOS Logic Gates 1.2 Simple CMOS Logic Gates 1.3 Computer Simulation 1.4 Transfer Curves and Noise Margins 1.5 Gate Delays and Rise and Fall Times 1.6 Transient Response 1.7 An RC Approximation to the Transient Response of a CMOS Inverter 1.8 Summary 1.9 Bibliography 1.10 Problems 2. PROCESSING, LAYOUT, AND RELATED ISSUES 2.1 CMOS Processing 2.2 Bipolar Processing 2.3 CMOS Layout and Design Rules 2.4 Advanced CMOS Processing 2.5 Bibliography 2.6 Problems 3. INTEGRATED-CIRCUIT DEVICES AND MODELING 3.1 Simplified Transistor Modeling 3.2 Semiconductors and pn Junctions 3.3 MOS Transistors 3.4 Advanced MOS Modeling 3.5 Bipolar-Junction Transistors 3.6 SPICE-Modeling Parameters 3.7 Appendix 3.8 SPICE Simulations 4. TRADITIONAL MOS DESIGN 4.1 Pseudo-NMOS Logic 4.2 Pseudo-NMOS Logic Gates 4.3 Transistor Equivalency 4.4 CMOS Logic 4.5 CMOS Gate Design 4.6 SPICE Simulations 4.7 Bibliography 4.8 Problems 5. TRANSMISSION-GATE AND FULLY DIFFERENTIAL CMOS LOGIC 5.1 Transmission-Gate Logic Design 5.2 Differential CMOS Circuits 5.3 Bibliography 5.4 Problems 6. CMOS TIMING AND I/O CONSIDERATIONS 6.1 Delay of MOS Circuits 6.2 Input/Output Circuits 6.3 Bibliography 6.4 Problems 7. LATCHES, FLIP-FLOPS, AND SYNCHRONOUS SYSTEM DESIGN 7.1 CMOS Clocked Latches 7.2 Flip-flops 7.3 CMOS Flip-flops 7.4 Synchronous System Design Techniques 7.5 Synchronous System Examples 7.6 Bibliography 7.7 Problems 8. BIPOLAR AND BICMOS LOGIC GATES 8.1 Emitted-Coupled Logic Gates 8.2 Current-Mode Logic 8.3 BiCMOS 8.4 SPICE Simulations 8.5 Bibliography 8.6 Problems 9. ADVANCED CMOS LOGIC DESIGN 9.1 Pseudo-NMOS and Dynamic Precharging 9.2 Domino-CMOS Logic 9.3 No-Race-Logic 9.4 Single-Phase Dynamic Logic 9.5 Differential CMOS 9.6 Dynamic Differential Logic 9.7 Bibliography 9.8 Problems 10. DIGITAL INTEGRATED SYSTEM BUILDING BLOCKS 10.1 Multiplexors and Decoders 10.2 Barrel Shifters 10.3 Counters 10.4 Digital Adders 10.5 Digital Multipliers 10.6 Programmable Logic Arrays 10.7 Bibliography 10.8 Problems 11. INTEGRATED MEMORIES 11.1 Static Random-Access Memories 11.2 Static Random-Access Memory Storage Cells 11.3 Address Buffers and Decoders 11.4 Dynamic Bus Precharge and Address-Transition-Detect Circuits 11.5 Modifications for Large Static Random-Access Memories 11.6 Dynamic Random-Access Memories 11.7 Read-Only Memories 11.8 Bibliography 11.9 Problems 12. GAAS DIGITAL CIRCUITS 12.1 Introduction 12.2 GaAs Processing and Components 12.3 MESFET Modeling 12.4 MESFET Second-Order Effects 12.5 Logic Design with MESFETs 12.6 Capacitively Enhanced Logic 12.7 GaAs Logic Family Comparison 12.8 Heterojunction Bipolar Technology 12.9 Bibliography 12.10 Problems 13. DIGITAL SYSTEM TESTING 13.1 Conservative Design Principles 13.2 Scan-Design Techniques 13.3 Localized Test-Vector Generation and Test-Output Compression Techniques 13.4 Boundary-Scan Testing 13.5 Bibliography 13.6 Problems