Abstract
This paper presents a novel methodology to obtain the entire power consumption versus delay tradeoff curve for the critical paths of a combinational logic circuit in a very efficient way using the genetic algorithm (GA). In order to evaluate the proposed algorithm the most representative set of two-level and multi-level networks from the MCNC91 benchmark suite were processed. The required computational effort, measured in terms of CPU time, is several times better for the proposed GA optimization technique than liner programming (LP) technique. On the other hand, the optimal design points obtained by the GA and LP techniques are very close to each other to within 0.3%.
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