Diffused Metal Oxide Semiconductor Research Articles

On the improved RF performance of step field plate LDMOS transistor

This paper presents an analysis of the Step Field Plate Laterally Diffused Metal Oxide Semiconductor (SFP LDMOS) structure for improved high power and RF performance. The proposed structure is cost-effective, CMOS integrable, and has a high power figure of merit (FoM) due to its high off-state breakdown voltage (BVDS,off) and low specific on-resistance (Rsp). Significant improvement in frequency behavior is observed, as demonstrated by the flatter trans-conductance (gm), 12.5x lower gate-to-drain capacitance (Cgd), 2.5x lower gate-to-source capacitance (Cgs), and lower output conductance (gds). Single tone and double tone analyses are performed on an RF PA circuit implemented in TCAD. Results show ∼5 dBm higher output power (Pout), ∼6 dB higher power gain, and 46% higher drain efficiency (η), which are attributed to ∼1.9x lower drain-to-source capacitance (Cds) and ∼15 dBm lower magnitude of third-order intermodulation distortion due to lower third order derivative of drain current (ID). The paper also explains the device physics behind these observations.

In0.53Ga0.47As/In0.52Al0.48As Quantum Well Step Gate LDMOS to Improve the Device Performance

In this work, a new laterally double diffused metal oxide semiconductor (LDMOS) using In0.53Ga0.47As/In0.52Al0.48As Quantum well (QW) layer with a p-well step gate has been proposed. In the proposed device structure, the gate region splits into three steps in which the oxide thickness increases from the source to the drain end. As the gate insulator width varies from source to drain end, it results in better control of the gate over the channel and also a reduction in the gate-to-drain capacitance (CGD). These features offer higher transconductance with reduced switching delays, which makes the device appropriate for RF applications. Again, the concentration of current in the channel section is enhanced due to the presence of the Quantum well region and the InP spacer layer, which drastically reduces the On-resistance. But, the device achieves lesser gate-to-drain capacitance which results in decrease in the switching speed. On the other hand the proposed device offers less gate charge with the low value of CGD gives minimised switching loss. Based on 2D TCAD simulation, the proposed QW LDMOS exhibits 70% improvement in On-resistance, 45% in breakdown voltage, 84% improvement in peak transconductance, 26% improvement in switching delay, and 19% improvement in gate charge density as compared to conventional In0.53Ga0.47As devices.

A simple Monte Carlo model for performance optimization of single photon avalanche diode

Single photon avalanche diode (SPAD) has the advantage of high internal gain, which is widely used in fluorescence detection and quantum communication. The high internal gain of the device is mainly due to avalanche multiplier effect. Therefore, it is of great significance to study avalanche multiplication effect for the design and performance optimization of SPAD devices. In this paper, a Simple Monte Carlo (SMC) model is implemented based on MATLAB, which includes interval phonon scattering and impact ionization of carriers. In this model, the electric field at different reverse bias voltages is extracted based on Technology-Computer- Aided- Design (TCAD). The model simulates the energy, velocity and impact ionization of carriers in the depletion region. The model has been verified on SPAD devices fabricated by 0.18um Bipolar - Complementary Metal Oxide Semiconductor - Diffused Metal Oxide Semiconductor (BCD) process. The SMC model simulates the dependence of the avalanche multiplication gain and excess noise factor of the SPAD device on the reverse bias voltage. In addition, the SMC model estimates the current–voltage (IV) characteristics and avalanche breakdown voltage of the device. In conclusion, the SMC model can provide guidance for the design and performance optimization of SPAD devices.

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.

Influence of Hot Carrier Degradation on the Characteristics of a High-Voltage SOI Transistor with a Large Drift Region

The results of studying the effect of hot carrier degradation on the electrical characteristics of high-power laterally diffused metal oxide semiconductor (LDMOS) transistors made according to the silicon-on-insulator (SOI) technology, with a long drift region with topological norms of 0.5 microns, are discussed. The analysis of the degradation of hot carriers in high electric fields is based on the experimental results and the additional use of an analytical model. The physical origin of this mechanism is related to the formation of traps at the Si/SiO2 interface. With the help of numerical analysis and experiments, the electrical character-istics of SOI nLDMOS transistors are considered in a wide range of control voltages in order to study their effect on the safe operation zone and reliability of the device under conditions of the degradation of hot carriers. The results of these studies allow us to conclude that a 20% expansion of the safe operation zone is possible.

Research on the newest GaN-Based solid-state power amplifier for CiADS project

Institute of Modern Physics (IMP), Chinese Academy of Sciences is the first domestic institute to widely apply solid-state power amplifier (SSPA) to linear accelerator project from China Accelerator Driven Sub-critical System (C-ADS) project started since 2011. Until now, SSPA design has already been considered for two large-scale scientific facilities in Guangdong Province of southeast China: China initiative Accelerator Driven System (CiADS) and High Intensity Heavy-ion Accelerator Facility (HIAF). The SSPA was developed rapidly due to the reliable technologies of LDMOS-based (laterally diffused metal oxide semiconductor) power amplifiers.With the maturation of GaN (Gallium Nitride) technology, GaN-based amplifiers have been studied in the field of accelerators since 2020. Last year, IMP made new progress with GaN SSPA, measuring power modules at three fundamental frequency points of 162.5 MHz, 325 MHz, and 650 MHz. The first 50 kW rack with GaN SSPA was measured at 650 MHz in IMP, and its modules offer huge advantages of 40% output power and 8% efficiency compared to the newest LDMOS at the same frequency, which holds a fascination for our project.Until the beginning of 2023, the prototype power modules on three frequency points were completed and tested. This paper will detail the design development of GaN technology and its technical characteristics.

Surrogate models for device design using sample-efficient Deep Learning

Generation of training dataset for machine learning-based device design algorithm is expensive. To address this, we propose an active learning approach. Its efficiency is demonstrated through a Deep Neural Network (DNN) based Laterally Diffused Metal Oxide Semiconductor Field-effect Transistor (LDMOSFET) off-state breakdown voltage (BVDS,off) and specific on-resistance (Rsp) predictor. Our results show the possibility of ∼50% reduction in the training dataset size without compromising the baseline accuracy. Specifically, we compared eight sampling techniques and found that Informative-Query by Committee (I-QBC) and Diverse Informative-Greedy Sampling (DI-GS) techniques work best with ∼1.87% Euclidean Norm of Prediction Error (ENPE).

Comprehensive study of the radiation effects on the LDMOS transistors

The reliability of power devices is attracting more and more attention, especially in the extreme radiation environment. The laterally diffused metal–oxide–semiconductor (LDMOS) has been widely used in high voltage integrated circuits. In this paper, the radiation effects of LDMOS transistors are extensively investigated through three-dimensional (3D) TCAD simulations, including Total-Ionizing Dose (TID), Single-Event Effect (SEE) and Transient Dose Rate Effect (TDRE). Firstly, the mechanism of TID effect on the LDMOS is revealed in consideration of temperature variations. Secondly, the single-event effect of the LDMOS is studied with different incident positions, linear energy transfer (LET) values, incident lengths, incident angles, bias conditions and temperatures. Besides, the combined effect of total-ionizing dose and single-event burnout is characterized. Finally, transient response of the LDMOS under transient γ radiation is also studied comprehensively. Therefore, it gives an insight into the physical mechanisms and response characteristics of complex radiation effects, which can provide guidance for radiation-hardened by design and application of the LDMOS devices.

Analysis of impact ionization on RF power LDMOS reliability under RF life test in radar system

This paper focuses on correlation between the electrical parameter shifts and the failure phenomena that appeared after pulsed RF life tests applied to RF power LDMOS transistor (Radio Frequency Laterally Diffused-Metal–Oxide–Semiconductor). The results of the test bench (radar circuit) are measured in real time. The failure rate is more significant at low temperatures after the aging life test. The electrical performances are shifted, notably, IGS, VTH, GM, RDSON, CRSS, gain, and S-parameter S21. A 3D physical simulation (SILVACO-TCAD) is used to highlight the phenomena linked to the characteristic's degradation. The impact ionization induces physical degradations in the study of transistors, which are manifested by a variation in their electrical performance. It showed that the located failure zone is due to the device's shifted characteristics, which are deeply correlated with the structure area. The goal of the paper is to prove the failure mechanism through the characteristics evaluation origin, that is started by the carrier generation, because of the impact ionization phenomenon. The demonstration is based on the physical simulations are conducted at RF power NLDMOS. The outcomes show that the mechanism is due to the augmented carrier injection into the advanced silicon dioxide layer (SiO2) or/and in the Si/SiO2 interface state. The consistency between the physical simulations and experimental results emphasizes the theoretical analysis performed in this work.

Novel Step Field Plate RF LDMOS Transistor for Improved BVDS-R on Tradeoff and RF Performance

In this article, a novel step field plate (SFP) laterally diffused metal–oxide–semiconductor (LDMOS) structure is proposed for improved breakdown voltage- ON resistance tradeoff and better RF performance. The proposed structure could be easily integrated into the CMOS process flow using four additional noncritical masks. The known materials like fully silicided polysilicon and silicon nitride (SiN) are used as FP and dielectric, respectively. The proposed design improves the device performance by uniformly distributing the electric field in the drift region. The higher drift doping for the same OFF-state breakdown voltage improves the ON resistance by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2.5\times $ </tex-math></inline-formula> and ON-state breakdown voltage by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2\times $ </tex-math></inline-formula> . Significant improvements in frequency behavior and flat power response are also observed. The device physics behind different observations are explained using detailed TCAD simulations.

The Root Cause Behind a Peculiar Dual-Mode ON-State Breakdown in High Voltage LDMOS

This work investigates the often-observed current discontinuity much before avalanche breakdown (dual-mode ON-state breakdown) in the output characteristics of a laterally diffused metal–oxide–semiconductor (LDMOS) device. The physical origin of the dual-mode ON-state breakdown, often reasoned to be due to parasitic n-p-n, is shown to be independent of parasitic n-p-n. A laterally diffused tunnel FET (LDTFET) with a drift region profile same as LDMOS was experimented to rule out the effect of parasitic n-p-n. LDTFET device, which intrinsically cannot have parasitic n-p-n, also shows similar output characteristics with dual-mode ON-state breakdown. This proved that the parasitic bipolar turn-on is not the root cause behind the observed behavior. On the contrary, it was found to be dependent on the onset of space charge modulation (SCM) in the drift region, resulting in localized high electric field and quasi-saturation effects at low drain voltages. The effect of mobility degradation due to the high electric field in the drift region post-SCM is also presented, emphasizing that the observed behavior results from the high field mobility degradation of majority charge carriers.

Design and implementation of an S-band transmitter for nanosatellites with new configuration

In this paper, the author presents the design and implementation of an Sband transmitter for nanosatellites. By combining heterostructure field effect transistors (HFET) and laterally diffused metal–oxide–semiconductor (LDMOS) technology and using flexible structure and flexible control method, this research obtained 60 dB gain power when input is -14 dBm, output power is 46 dBm (more than 25 W) in 2,1 GHz -2,3 Ghz frequency; phase noise is -80 dBc/Hz at 100 KHz offset frequency. Unlike other traditional transmitters, this transmitter was designed with multi-stages which have multi-peaks resonance to expand bandwidth to respond to the requirement of generation of the complex signal in wide band. Moreover, the phase locked loop (PLL) in frequency synthesizer makes the frequency conversion more flexible and output frequency more stable; thermal problem in module also was solved by using thermistor and operation mode. Measurement results prove that the design does not only satisfy the requirements of nanosatellites but also can be applied to other satellites together with their ground station because it has open configure with flexible structure and flexible control method.

A 15 V-Tolerant and Radiation-Hardened MOSFET Driver With Positive and Negative References

Radiation-hardened and high-voltage power circuits are key components in aerospace applications. However, when working at high voltages, the effects of the total ionizing dose (TID) and the single event limit the application of power driving circuits in a radiation environment. A 15 V-tolerant radiation-hardened MOSFET driver was designed. The circuit architecture, which is based on positive and negative references, can reduce the gate source voltage of the transistors to less than 5&#x00A0;V, allowing the selection of thin-gate oxide high-voltage transistors. On this basis, adopting enclosed layout transistor (ELT) N-channel metal oxide semiconductor (NMOS) transistors helps the driver to obtain a good resilience to TID hardness. Additionally, this work optimized the layout of high-voltage N-type laterally diffused metal oxide semiconductor (LDMOS) transistors in the driver to effectively improve the single-event burnout (SEB) threshold. Three chips with different N-type drift region lengths were designed and fabricated in a 0.35&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu m$</tex-math></inline-formula> BCD process. The test results showed that the TID hardening capability of these chips with ZENER references and ELT NMOS transistors all exceeded 100 krad (Si). In addition, this driver was tested under heavy ion irradiation with linear energy transfer (LET) exceeding 75 MeV&#x00B7;<inline-formula><tex-math notation="LaTeX">$\dot\mathrm{{c}}{\mathrm{{m}}^{2}}\mathrm{{/mg}}$</tex-math></inline-formula>. The results show that this driver with a 6.6&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu m$</tex-math></inline-formula> drift region length had no single event latchup (SEL), single event gate rupture (SEGR), or single event burnout (SEB) sensitivity.

A novel SOI-LDMOS with field plate auxiliary doping layer that has improved breakdown voltage

Field plate (FP) is a widely used electric field optimization technique in lateral power devices. However, we found that the electric field distribution optimized by FP still has poor uniformity due to the excessive induced charges at the end of FP. To solve the problem, a novel silicon on insulator based lateral double diffused metal oxide semiconductor (SOI-LDMOS) with a field plate auxiliary doping layer (FPADL) is proposed. Our investigation proved that the FPADL introduces an additional part of space charge and partially balances the excessive induced charges at the end of FP. As a result, the FPADL introduces an additional electric field peak and improves the electric field distribution. Thereby, the SOI-LDMOS with FPADL has improved breakdown voltage (BV). The effect of FPADL is verified experimentally. In our experiment, the FPADL is realized by modifying the mask of buffer layer to avoid increasing the process cost. The measurement results showed that, comparing with the conventional SOI-LDMOS with FP, the proposed SOI-LDMOS with FPADL improved the BV by 9.52% with the on-resistance and the process cost maintained. Therefore, the proposed SOI-LDMOS with FPADL is a promising device.

Design considerations of a novel Triple Oxide Trench Deep Gate LDMOS to improve self‐heating effect and breakdown voltage

In this study, design considerations of a new device structure are presented to improve the self-heating effect (SHE) and the breakdown voltage of the Deep Gate LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) transistor and compared with a conventional LDMOS (C-LDMOS). In this case, triple oxide trenches with an N+ trench are embedded in the drift region. These trenches create additional peaks in the electric field profile, so the electric field is modified. The authors demonstrate that by optimising the trenches, the breakdown voltage of the device increases. Also, a partially buried oxide is used in the proposed structure to create a conduction path that significantly reduces the SHE. Moreover, the results indicate that the specific on-resistance, lattice temperature, and breakdown voltage of the proposed device are improved considerably compared to the C-LDMOS.

Drain Side Area-Modulation Effect of Parasitic Schottky Diode on ESD Reliability for High Voltage P-Channel Lateral-Diffused MOSFETs

This letter focused on the additive effect of horizontal Schottky diodes on the drain side of a high-voltage p-channel laterally diffused metal–oxide–semiconductor (pLDMOS). These components were evaluated using transmission-line pulse and human body model (HBM) tests. When the parasitic Schottky area at the drain was smaller, the Schottky characteristics were less obvious; the device’s current mostly flowed through the heavily doped $\text{P}^{+}$ area, and the improvement in ${I}_{\text {t2}}$ was minor. When the parasitic Schottky area covered more than 60% of the drain side, the Schottky area accounted for the majority of current flow; therefore, the electrostatic discharge current could flow more evenly. These modified pLDMOSs can withstand higher voltages because of their parasitic Schottky diodes and higher impedance. In addition, their ${I}_{\text {t2}}$ values are superior to those of normal pLDMOSs. With the drain side of the pLDMOS completely covered by Schottky diodes, the device produced the highest ${I}_{\text {t2}}$ value of 1.659 A (130.4% higher than that of the reference sample), an HBM value of 5 kV (300% higher than the reference), and an improved holding voltage (4% greater than that of the reference).

Analytical breakdown voltage model for a partial SOI-LDMOS transistor with a buried oxide step structure

We have developed a simple physics-based two-dimensional analytical off-state breakdown voltage model of a partial buried oxide step structure (PBOSS) silicon-on-insulator laterally diffused metal oxide semiconductor (SOI-LDMOS) transistor. The analytical model includes the expressions of surface potential and electric field distributions in the drift region by solving the 2D Poisson equation. The electric field at the Si–SiO2 surface is modulated by additional electric field peaks developed due to the presence of the PBOSS structure. The uniformly distributed electric field results in improved breakdown voltage. Further, the breakdown voltage is analytically obtained by means of the critical electric field concept, to determine the breakdown characteristics. The model reveals the impact of the critical device design parameters such as thickness and length of the PBOSS structure, doping, and thickness of the drift region on the surface electric field and the breakdown voltage. The proposed model is verified by ATLAS two-dimensional simulations. The analytical model will be useful to design high-voltage SOI-LDMOS transistors for power switching applications.

Deep neural network-based approach for breakdown voltage and specific on-resistance prediction of SOI LDMOS with field plate

Breakdown voltage (BV) and specific on-resistance (R on,sp), are critical indicators to measure the quality of the power device. To improve the device performance, field plate technology has been developed by modifying the electric field distribution. However, the current technology computer-aided design (TCAD) simulation cannot predict the effect of field plate on BV and R on,sp simultaneously, and the operation process is complicated. This paper proposes a deep neural network (DNN)-based model instead of TCAD to predict the effect of field plates on BV and R on,sp of silicon on insulator lateral double diffused metal oxide semiconductor. The experimental results show that, compared with TCAD simulation, the average deviation for BV and R on,sp is 5.06% and 2.55%, respectively. Also, the time for BV prediction is accelerated significantly up by 1.23 × 105. Our DNN model provides a potential direction to predict device performance with higher efficiency.

Capacitance–Voltage Technique Based on Time Varying Magnetic Field for VDMOSFET—Part II: Measurements and Parameter Extractions

In part I, we have proposed a new capacitance–voltage technique ${C}$ ( ${V}$ ), which is simultaneously based on external ac magnetic field for surface potential modulation and on dc voltage to sweep the gate voltage. In part II, we describe the parameter extractions of vertical double diffusion metal–oxide–semiconductor field effect transistor (VDMOSFET) devices, combining the capacitance characteristics of gate–source, ${C}_{\text {GS}}$ ( ${V}_{G}$ ) and gate–drain ${C}_{\text {GD}}$ ( ${V}_{G}$ ), measured using the above cited technique, with those measured conventionally. In doing so, we have been able to extract semiconductor capacitance ( ${C}_{\text {SC}}$ ), interface trap capacitance ( ${C}_{\text {it}}$ ), doping profile concentration ${N}$ ( ${x}$ ), and interface trap density ${D}_{\text {it}}$ ( ${E}$ ) of different regions of VDMOSFET.

A Ultra-Low Specific On-Resistance and Extended Gate SJ LDMOS Structure

A new structure of extended gate (EG) SJ LDMOS is proposed in this paper to overcome the substrate assisted depletion (SAD) effect in the structure of Super-Junction lateral double diffused metal oxide semiconductor (SJ LDMOS). Different from other surface SJ structures, the SJ layer of the structure is located in the body of the drift region. Gate oxide and silicon layer form the EG Structure-Oxide-Semiconductor structure that is similar to Metal–Insulator–Semiconductor capacitor. The the N-drift of the EG structure can obtain the charge compensation to overcome the SAD effect, and a nearly rectangular electric field is achieved. In the on-state, the EG structure has two conductive channels and the accumulation layer is formed on the drift region. By accumulating high concentration electrons in the channels, the specific on-resistance (RON,sp) is greatly reduced. When the drift length is 24 μm, 431.4 V breakdown voltage (VB) and 9.8 mΩ cm2 RON,sp are achieved, and the figure of merit is 18.9 MW cm−2.