Diffused Metal Oxide Semiconductor Research Articles

A new low specific on-resistance Hk-LDMOS with N-poly diode

A new structure of the laterally diffused metal–oxide–semiconductor transistors (LDMOS) using a high permittivity (Hk) dielectric is proposed, and its mechanism is investigated by 2-D TCAD simulation. The breakdown voltage (BV) is remarkably increased by using the Hk dielectric. Moreover, a reverse biased poly diode is first introduced on the Hk dielectric, which assists the n-drift region forming an electron accumulation layer to reduce the specific on-resistance (Ron,sp) further. Compared with a conventional LDMOS with the same geometry, the BV increases by 24%, and the Ron,sp decreases approximately by 50%. Besides, the proposed structure is less sensitive to the n-drift region doping deviation, and exhibits a larger safe operating area (SOA).

An Accumulation Mode RF Laterally Double Diffused MOSFET With Improved Performance

In this letter, an improved radio frequency (RF) laterally double diffused metal–oxide–semiconductor (LDMOS) transistor with the application of accumulation mode stripe (AMS) is proposed and fabricated in a 0.35- $\mu \text{m}$ CMOS process without extra process steps or masks. AMS accumulates electrons at the surface of the drift region, which result in an improvement in the saturated drain current. Moreover, AMS modulates the electric field distribution across the drain extension region by inducing an electric field peak at its edge. Power performances at 3.1 GHz for the AMS-LDMOS show a 0.75-W/mm continuous-wave output power density with 21-dB linear gain and over 52% drain efficiency at a supply voltage of 32 V. In comparison with conventional RF LDMOS with source field plate, the proposed device exhibits 1–1.5 dB higher linear gain along with improved linearity.

ESD protection design and enhancement in the power 60‐V n‐channel LDMOS by embedded‐SCR anode islands

An electrostatic discharge (ESD) strengthening design of high-voltage (HV) n-channel laterally diffused metal–oxide semiconductor (nLDMOS) transistors combined with embedded-SCR anode islands is investigated. After a systematic layout implementation and analysis, the anti-ESD robustness [or secondary breakdown current (It2)] of drain pnp-arranged and SCR isolated-type DUTs were higher than 7-A (ESD reliability improvements of these nLDMOS-SCR devices were more than 282.5% (199.2%) higher than that of the pure nLDMOS (pnp-stripe) component. Also, it can be found that the ESD robustness of the pnp-arranged type is greater than the npn-arrangement. Therefore, an adequate architecture of an HV nLDMOS device embedded with an SCR (pnp-arranged) and SCR isolated manner can gain high ESD-reliability immunity.

Evolution study of the ElectroMagnetic Interference for RF LDMOS in series chopper application after thermal accelerated tests

The temperature is a critical parameter, for proper functioning of a system or a circuit, particularly in RF electronic devices. It considerable influence on reliability and performances; consequently plays an essential part in failure mechanisms and in lifetime. Recent studies have been focused in ElectroMagnetic Interferences (EMI) evolution after accelerated ageing tests and their effects on robustness behaviours (static, dynamic and RF). Even rarer to use RF devices in a power application.This paper deals with the (EMI) evolution of conducted interferences in common and differential mode of RF LDMOS (Radio Frequency Lateral Diffused Metal–Oxide–Semiconductor) devices applied to a series chopper. In addition their influences on the electrical parameters are studied after various thermal accelerated ageing tests. The experimental results (spectre and waveform parameters) are presented and discussed. The obtained measurements have highlighted that there is a clear increase in the amplitude of resonances on the interference spectra after ageing. The evolution is not the same for all the parameters and for the different thermal tests. The shift is proportional to temperature. To reach a better understanding of the physical mechanisms of parameter’s shift after thermal tests, a numerical model (Silvaco-Atlas) was employed to confirm the degradation phenomena. Actually, the charge trapping in the gate oxide causes a decrease in the Miller capacity value (Crss), thereafter in turn a decrease in the disturbances level.

Frequency Analysis and Multiline Implementation of Compensated Impedance Inverter for Wideband Doherty High-Power Amplifier Design

In this paper, we present a frequency analysis of a compensated impedance inverter and its effective implementation in the context of high-power Doherty amplifier (DPA) design. On the basis of an idealized DPA model, we calculate the expected operative bandwidth and the corresponding maximum drain efficiency as a function of the modulated signal statistics. In addition, we introduce an effective technique for the implementation of the compensated impedance inverter, suitable for preserving its broadband characteristics in the presence of large device’s output capacitance. The implementation technique is based on the generalized equivalent transmission-line equivalence principle, which considers both shortening and lengthening the equivalent transmission lines. We demonstrate that, by the proposed approach, parasitic absorption is possible maintaining a low $Q$ -factor of the equivalent network. The technique is validated by the development of a silicon laterally diffused metal–oxide–semiconductor DPA with optimized peak power and efficiency for applications in the 650–950-MHz band. The fabricated prototype is characterized by an LTE signal with a 20-MHz bandwidth and peak-to-average-power ratio of 7.5 dB and features an average drain efficiency between 37% and 47%, with an average power of 49 dBm across 37.5% of the bandwidth.

Impacts of ESD Reliability by Different Layout Engineering in the 0.25-μm 60-V High-Voltage LDMOS Devices

AbstractHow to effectively enhance the reliability robustness in high-voltage (HV) BCD [(bipolar) complementary metal-oxide semiconductor (CMOS) diffusion metaloxide semiconductor (DMOS)] processes is an important issue. Influences of layouttype dependences on anti-electrostatic discharge (ESD) robustness in a 0.25-μm 60-V process will be studied in this chapter, which includes, in part (1), the traditional striped-type n-channel lateral-diffused MOSFET (nLDMOS), waffle-type nLDMOS, and nLDMOS embedded with a “p-n-p”-arranged silicon-controlled rectifier (SCR) devices in the drain side; and in part (2) a p-channel LDMOS (pLDMOS) with an embedded “p-n-p-n-p”-arranged-type SCR in the drain side (diffusion regions of the drain side isP+-N+-P+-N+-P+). Then, these LDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (Vt1), holding voltage (Vh), and secondary breakdown current (It2). Eventually, the sketching of the layout pattern of a HV LDMOS is a very important issue in the anti-ESD consideration. Also, in part (1), the waffle-type nLDMOS DUT contributes poorly to It2robustness due to the non-uniform turned-on phenomenon and a narrow channel width per unit finger. Therefore, the It2robustness of a waffle-type nLDMOS device is decreased about 17% as compared to a traditional striped-type nLDMOS device (reference DUT-1). The ESD abilities of traditional stripedtype and waffle-type nLDMOS devices with an embedded SCR (“p-n-p”-manner arrangement in the drain side) are better than a traditional nLDMOS 224.4% in average. Noteworthy, the nLDMOS-SCR with the “p-n-p” -arranged-type in the drainend is a good structure for the anti-ESD reliability especially in HV usages. Furthermore, in part (2) this layout manner of P+discrete-island distributions in the drain-side have some impacts on the anti-ESD and anti-latch-up (LU) immunities. All of their It2values have reached above 6 A; however, the major repercussion is that the Vhvalue will be decreased about 66.7 ~ 73.7%.

A 280 W LDMOS broadband Doherty PA with 52% of fractional bandwidth based on a multi-line impedance inverter for DVB-T applications

We introduce a new technique for the design of an output combiner for Doherty power amplifier (DPA) and its effective exploitation for the development of a wideband laterally diffused metal oxide semiconductor (LDMOS) DPA. The design is enabled by a two-line impedance inverter for the DPA back-off operation, which is capable of 52% of fractional bandwidth. The technique is validated by the development of a DPA prototype for Ultra high frequency terrestrial digital video broadcast (DVB-T) applications, with optimized peak power and efficiency over 470–806 MHz. The prototype delivers between 40 and 53% of average efficiency across the band, at 49 dBm output power in average across the bandwidth, and supporting DVB-T signals with 8 MHz bandwidth and a peak-to-average power ratio of 10.5 dB. It achieves the target adjacent channel power ratio of −52 dBc at 750 MHz if digital pre-distortion is applied, and provides 47.8 dBm of output power with a drain efficiency of 44.3%.

Reliability Analysis of P+ Pickup on Anti-ESD Performance in Four CMOS Low-Voltage Technology Nodes

ABSTRACTN-channel metal-oxide semiconductor field-effect transistor (MOSFET) devices in I/O ESD protection circuits are often drawn in the parallel multi-finger construction. However, a non-uniform turned-on characteristic always occurs with this type of construction; i.e. the resulting sub-MOSFETs cannot be turned on at the same time. The ESD high-current will thus be conducted through a few turned-on MOSFETs, seriously impacting the ESD reliability and capability. On the source-side, the P+ pickup layout placement influence on an nMOSFET ESD capability of input/output pads for power-management popular 0.6- to 0.18-μm BCD (bipolar–complementary metal oxide semiconductor–diffusion metal oxide semiconductor) CMOS (complementary metal oxide semiconductor) technologies is investigated in this paper. However, the It2 decreasing percentage in an even- and full-adding type of P+ pickup stripe in the source end, as compared with that of a corresponding NonePickup Ref. type, is actually disadvantageous to the ESD immunity. The secondary breakdown current (It2) decreasing percentages have a range of 2.43%–63.31% for the four process nodes. This is very serious for the three technology nodes especially in the ultra-deep submicron 0.18-μm technology. On the contrary, the 0.35-μm technology is a critical process node. Furthermore, the figure of merit (FOM) for a device's ESD performance in a multi-finger type MOSFET can be used to well characterize and predict the device's It2 behaviour using an empirical methodology proposed in this work.

High-frequency performances of superjunction laterally diffused metal–oxide–semiconductor transistors for RF power applications

This paper presents the dc and high-frequency performances of laterally diffused metal–oxide–semiconductor (LDMOS) transistors with superjunction (SJ) structures. The SJ-LDMOS transistors were fabricated using a 0.5-µm CMOS process. By utilizing a modified SJ/RESURF layout (Type I) or a tapered SJ layout (Type II) in our devices, better high-frequency performances and higher breakdown voltages are achieved compared with conventional SJ counterpart, owing to the suppression of the substrate-assisted depletion effect and the reduction of the drain resistance. For Type I device with an optimal SJ layout dimension, the cutoff frequency and the breakdown voltage are 3.7 GHz and 68 V, respectively. For Type II device with a smallest p-pillar width near the drain, they can be enhanced further and reach to 4.9 GHz and 83 V. These experimental results suggest that the SJ-LDMOS can be used in the RF power amplifiers.

Effect of Scaling Parameters of Laterally Double Diffused Metal Oxide Semiconductor Device on Drain Induced Barrier Lowering

Effect of Scaling Parameters of Laterally Double Diffused Metal Oxide Semiconductor Device on Drain Induced Barrier Lowering

Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer**Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079) and the Fundamental Research Funds for the Central Universities, China (Grant No. ZYGX2014Z006).

A new ultra-low specific on-resistance (Ron,sp) vertical double diffusion metal–oxide–semiconductor field-effect transistor (VDMOS) with continuous electron accumulation (CEA) layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration (Nn). In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp. Especially, the two PN junctions within the trench gate support a high gate–drain voltage in the off-state and on-state, respectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS (CSJ-VDMOS) at the same high breakdown voltage (BV).

Design and optimization of LDMOS-SCR devices with improved ESD protection performance

The lateral diffusion metal-oxide semiconductor embedded silicon controlled rectifier (LDMOS-SCR) devices with optimized structures and layouts for improving the electrostatic discharge (ESD) protection ability have been proposed. The devices are designed and fabricated in 0.25-μm, 0.35-μm and 0.5-μm Bipolar-CMOS-DMOS processes. Firstly, by designing an appropriate stripe resistance in series with the source of the LDMOS-SCR, the holding voltage of the proposed high resistance LDMOS-SCR (HRLDMOS-SCR) increases. Secondly, by inserting a floating Zener-diode into the LDMOS-SCR, the trigger voltage of the modified Zener-diode triggered LDMOS-SCR (ZTLDMOS-SCR) decreases. Finally, the ZTLDMOS-SCR is further optimized by using a ring layout and incorporating a square source resistance, resulting in a significantly improved figure of merit in comparison to traditional LDMOS-SCR devices. The optimized ZTLDMOS-SCR devices are very attractive for constructing effective and latch-up immune high voltage ESD protection solutions in power integrated circuits.

New folding lateral double diffused metal oxide semiconductor breaking silicon limit with ultra‐low specific on‐resistance

A new lateral double diffused metal oxide semiconductor (LDMOS) is proposed for the first time with the step oxide layer above the folding silicon substrate. Three technologies, including of the electric field modulation effect, majority carrier accumulation, and folding silicon, are applied simultaneously to the proposed LDMOS for improving the trade-off between the breakdown voltage (BV) and specific on-resistance (R on,sp). The majority carrier accumulation layer under the extended gate is formed in the folding silicon substrate during the on-state operation. The high-doping drift region can be depleted completely in the off-state, thanks to an additional electric field modulation, which is analogous to the super junction idea. The uniform lateral electric field has been obtained due to the new electric field peak to improve the trade-off between the BV and R on,sp. The proposed LDMOS shows the R on,sp of 0.32 mΩ cm2 with the BV of 62 V, which has broken the silicon limit relationship with R on,sp of 2.0 mΩ cm2 under the same BV in the conventional LDMOS. This is the previously reported lowest R on,sp with the BV of about 60 V.

Investigation on LDMOS-SCR with high holding current for high voltage ESD protection

We investigate a novel lateral diffused metal-oxide semiconductor (LDMOS) device embedded in silicon controlled rectifier (SCR) and resistance-capacitance circuit (LDMOS-SCR-RC). The internal RC-coupling effect helps to increase the holding current (Ih), resulting in the enhanced latch-up immunity of electrostatic discharge (ESD) protection device in high voltage integrated circuits (HV ICs). Transmission line pulse testing results show that the proposed LDMOS-SCR-RC has the largest Ih and smallest trigger voltage (Vt1), comparing to the conventional LDMOS-SCR and LDMOS-SCR embedded a resistance. When key parameters such as the gate-length and resistance are optimized, the Ih increases further from 1.1A to 1.5A, while the Vt1 changes insignificantly. The detailed internal mechanism of LDMOS-SCR-RC with regard to key parameters is analyzed numerically by the SENTAURUS simulation. Results confirm that the increased Ih is mainly due to the enhanced RC-coupling effect. Finally, DC measurements conducted with a semiconductor curve tracer also confirm that the LDMOS-SCR-RC with small device area is effective for avoiding latch-up risks. The optimized LDMOS-SCR-RC provides a useful latch-up immune ESD protection solution for HV ICs input/output ports.

The effect of void on characteristics of LDMOS power amplifier

ABSTRACTThe effect of void on characteristics of the laterally diffused metal oxide semiconductor (LDMOS) power amplifier (PA) is analyzed using the thermal and circuit analysis together. Thermal analysis is performed for finding the junction temperature of LDMOS PA as void area changes. Circuit analysis is performed from these results and LDMOS PA libraries. The analysis results show the linearity, gain, and efficiency degradation in the LDMOS PA as a result of the increase in void area. And this simulation methodology can be used for the design of the PA. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:691–694, 2016

The use of interface-sensitive test structure comprising of shallow trench isolation as a tool for analyzing the quality of Si–SiO2 interfaces

Si–SiO2 interface plays an important role in the performance of VLSI devices. Minor changes in interfaces, which cannot be detected by direct measurements, can alter the electrical performance of sensitive devices, for example CMOS Image Sensors (CIS). In such cases, there is a significant time delay (up to several months) between the processing of the interface and the monitoring of its quality. In what follows, we describe herein a method for analyzing the quality of Shallow Trench Isolation (STI) interface based on analyzing the performance of a simple STI interface named as Sensitive High Resistance Structure (SSHR). This testing device can be introduced in the production line as a “short loop” monitoring device. The method was demonstrated by comparing various cleaning treatments while analyzing the resistivity and breakdown voltage of the SSHR device. Results were correlated with STI-sensitive final products such as CIS and Lateral Diffused Metal Oxide Semiconductor (LDMOS) transistors.

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET**Project supported by the Fund from the Ministry of Education, Science and Technological Development of the Republic of Serbia (Grant Nos. OI-171026 and TR-32026) and the Ei PCB Factory, Niš.

In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.

Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests

This paper investigates the effects of hot carrier injection on the switching performance of power RF LDMOS (Radio Frequency Lateral Diffused Metal–Oxide–Semiconductor) devices. In addition, their influences on the dynamic parameters are studied after various accelerated aging tests (thermal and electrical). The response of these parameters and the switching waveform are described. The findings of experimental results are presented and discussed. Measurements show that important variations are obtained on the devices' rise time. After aging tests, the charge trapping in the gate oxide causes the modifications in the Miller capacity level and width resulting in an increase of the rise time and a decrease in the fall time, consequently increasing of the switching losses.

A novel lateral diffused metal oxide semiconductor (LDMOS) by attracting the electric field Lines

In this paper, a novel silicon on insulator (SOI) lateral diffused metal oxide semiconductor (LDMOS) transistor with high voltage and high frequency performance is presented. In this work we try to reduce the electric field crowding in the drift region. The proposed structure consists of a metal in the buried oxide and also connected to the source. The inserted metal attracts the electric field lines in the buried oxide. It causes 67% improvement in the breakdown voltage in comparison with a conventional SOI-LDMOS (C-LDMOS). Our simulations with two dimensional ATLAS simulator show that the gate-drain capacitance improves in the proposed structure. The unilateral power gain also enhances. So, the proposed structure is suitable for high voltage and high frequency applications.

Pickup impact on high-voltage multifinger LDMOS–SCR with low trigger voltage and high failure current

The impact of inserting P+ pickup on high-voltage multi-finger laterally diffused metal–oxide–semiconductor–silicon-controlled rectifier (LDMOS–SCR) has been studied in this article. Four-finger LDMOS–SCR structures with finger length of 50μm using 0.5μm 18V complementarily diffused metal oxide semiconductor (CDMOS) process were fabricated and tested. Theoretical analysis is carried out to make detailed comparisons between LDMOS–SCR with and without P+ pickup. It verifies that the multi-finger LDMOS–SCR with P+ pickup has greater electrostatic discharge (ESD) robustness and effectiveness. Furthermore, transmission line pulse (TLP) test has been done and the results show that the trigger voltage (Vt1) of the LDMOS–SCR with P+ pickup remarkably decreases from 46.19 to 35.39V and the second breakdown current (It2) effectively increases from 8.13 to 10.08A.