Diffused Metal Oxide Semiconductor Research Articles

VDMOS electrical parameters potentially usable as mechanical state indicators for power VDMOS assemblies

Power device reliability is a multidisciplinary domain. It requires design and integration of sensors, implementation of signal processing algorithms that allow processing the different data provided by the different sensors in order to predict by statistical means the device failure occurrence and consequently anticipate the power device replacement. Currently, for device ageing studies in a laboratory, electrical measurements of device parameters are often used as an indicator of device ageing. Furthermore, smart metal-oxide semi-conductor technology integrates more and more sensors that permit to measure quantities such as on-state resistance or junction temperature of the device. In power vertical diffused metal oxide semiconductor (VDMOS) assemblies, it would be interesting to make use of the VDMOS electrical parameters deviations in order to monitor the ageing state of the power assembly. To that end, we carry-out in this paper a study mainly based upon electro-thermo-mechanical simulations in order to identify the power VDMOS electrical parameters that could be monitored in order to access to the mechanical state of the power assembly and therefore anticipate the assembly failure. The power VDMOS R on as well as zero temperature coefficient (ZTC) point are of interest because they are sensitive to mechanical stress. Consequently, in this paper, a procedure to minimise temperature impact on the Ron of the VDMOS transistor such that one could use the Ron as mechanical state indicator is shown. Another solution that makes use of a specific operating point of VDMOS (ZTC) which is temperature independent is also studied by simulations and experiment.

Application of a Ag Ductile Layer in Minimizing Si Die Stresses in LDMOS Packages

Lateral Diffused Metal Oxide Semiconductors (LDMOS) normally have a Cu-W flange, whose CTE is matched to Si. Low cost Cu substrate material provides 2X high thermal conductivity, and along with a AuSi eutectic solder is recommended for optimal thermal performance. However, the CTE mismatch between Cu and Si can lead to failure of the semiconductor as a result of die fracture, due to thermal stresses developed during the soldering step of the manufacturing process. Introducing a Ag ductile layer is very important in minimizing such thermal stresses and preventing catastrophic failure of the semiconductor. Ag is a ductile material electroplated on the Cu substrate to absorb stresses developed during manufacturing due to the CTE mismatch between Si and Cu. The Ag layer thickness affects the magnitude of the resulting thermal stresses. This study attempts to measure the yield strength of the Ag layer, and examines the optimal layer thickness to minimize die stresses and prevent failure. The yield stress of the ductile layer deposited on a Cu flange was measured by nanoindentation. The Oliver and Pharr method was applied to obtain modulus of elasticity and yield depth of Ag. A finite element analysis of the package was performed in order to map die stress distribution for various ductile layer thicknesses. The analysis showed that increasing the ductile layer thickness up to 0.01 - 0.02 mm, decreases the Si die stresses.

High temperature behavior of multi-region direct current current–voltage spectroscopy and relationship with shallow-trench-isolation-based high-voltage laterally diffused metal–oxide–semiconductor field-effect-transistors reliability

With the process compatibility with the mainstream standard complementary metal–oxide–semiconductor (CMOS), shallow trench isolation (STI) based laterally diffused metal–oxide–semiconductor (LDMOS) devices have become popular for its better tradeoff between breakdown voltage and performance, especially for smart power applications. A multi-region direct current current–voltage (MR-DCIV) technique with spectroscopic features was demonstrated to map the interface state generation in the channel, accumulation and STI drift regions. High temperature behavior of MR-DCIV spectroscopy was analyzed and a physical model was verified. Degradation of STI-based LDMOS transistors under high temperature reverse bias (HTRB) stress is experimentally studied by MR-DCIV spectroscopy. The impact of interface state location on device electrical characteristics was investigated. Our results show that the major contribution to HTRB degradation, in term of the on-resistance degradation, was attributed to interface state generation under STI drift region.

An area-efficient LDMOS-SCR ESD protection device for the I/O of power IC application

Lateral Double diffused Metal Oxide Semiconductor (LDMOS) transistors are widely used in HV output circuit and its Electrostatic Discharge (ESD) problem have been well studied. LDMOS embed Silicon Controlled Rectifier (LDMOS-SCR) can be used to improve LDMOS ESD robustness. In order to further enhance the ESD self-protection capability of LDMOS-SCR, a new device LDMOS-SCR with a floating P+implant region (FP-LDMOS-SCR) is proposed in this paper. Due to the floating P+implant region is placed near the drain end, It2 of the new FP-LDMOS-SCR device increases obviously, compared with traditional LDMOS and LDMOS-SCR devices. The FP-LDMOS-SCR′s It2 with one floating P+is 1.3A and that with two floating P+is 2.7A. The results of Technology Computer Aided Design (TCAD) simulations will be presented in this paper to help analysis the physical mechanism and observe the ESD behavior of the LDMOS-SCR. The proposed FP-LDMOS-SCR, same driver capability with LDMOS, can be applied in HV output circuit and also provide its ESD self-protection through shunted ESD stress to ground.

Power amplifier linearisation scheme to mitigate superfluous radiations and suppress adjacent channel interference

Power amplifiers are one of the costly devices in wireless communication systems and exhibit non-linearity. The problem of non-linearity in the power amplifier categorises in two disturbance impacts, output distortion and in-band distortion which lead to adjacent channel interference and constellation deviation, respectively. In order to gain maximum efficiency of the power amplifier and reduce interference, the authors propose a new digital pre-distortion scheme called complex gain convergence (CGC). The proposed scheme is compared with indirect learning architecture and validated against an laterally diffused metal oxide semiconductor (LDMOS) power amplifier. The outcome of applying CGC scheme shows enhancement in adjacent channel leakage ratio and error vector magnitude performance while the complexity is even lower. An experimental demonstration with the actual power amplifier is also presented.

A low on-resistance silicon on insulator lateral double diffused metal oxide semiconductor device with a vertical drain field plate

To reduce the on-resistance and enhance the breakdown voltage of silicon on insulator (SOI) lateral double diffused metal oxide semiconductor (LDMOS) device at the same time, a low on-resistance SOI-LDMOS device with a vertical drain field plate and trench gate and trench drain (VFP-TGTD-SOI-LDMOS) is proposed. The device has the features as follows: first, a trench gate and a trench drain are adopted, which can widen the vertical current conduction area, shorten the lateral current conduction path, and lower the on-resistance. Secondly, a vertical field plate is used, which modulates the electric field around it, reduces the high electric field at the end of the drain electrode, and increases the breakdown voltage. The VFP-TGTD-SOI device is compared with a conventional SOI device, a trench gate SOI device, a trench gate and trench drain SOI device with the same dimensional device parameters using the two-dimensional semiconductor simulator MEDICI. The results show that under the condition of their own highest figure of merit (FOM), the specific on-resistance value of the VFP-TGTD-SOI device is reduced by 53%, 23%, and increased by 87%, respectively and the breakdown voltage is increased by 4% and reduced by 9% and increased by 45%, respectively. By comparing the FOMs of the four structures, it can be seen that the VFP-TGTD-SOI device has the highest FOM, which indicates that among the four structures, it maintains the lower on-resistance and holds the higher breakdown voltage at the same time.

A novel partial-SOI LDMOSFET (>800 V) with n-type floating buried layer in substrate

In this paper, a novel high voltage lateral double diffused metal–oxide–semiconductor (LDMOS) field effect transistor based on partial silicon-on-insulator (PSOI) technology is proposed and investigated based on the numerical simulations. The structure is characterized by an n-type floating buried layer (NFBL) in the substrate under the silicon window near the drain. The buried layer in the substrate modulates the lateral and vertical electric field, which results in the electric field of the drift region distributed uniformly. Therefore, the breakdown voltage (BV) of the device is significantly improved. The influences of the key parameters on device performance of the proposed structure are discussed. Moreover, the self-heating effect (SHE) is greatly alleviated duo to the silicon window helps thermal conduction to the substrate, which improved the reliability of device application.

Physics-Based Low-Cost Test Technique for High Voltage LDMOS

This paper presents a low-cost test technique for testing high-voltage laterally diffused metal oxide semiconductor field effect transistor (HV-LDMOS) to identify structural defects such as gate-FOX breakdown, post breakdown thermal stress and drain leakage due to high voltages. A novel highly accurate hybrid MOS-p model for HV-LDMOS was developed and validated across various device geometries including both long and small gate-channels. Structural defects in HV-LDMOS were modeled and their physical effect was induced in the hybrid MOS-p model to develop fault models. These fault models were used for parametric testing and diagnosis of HV-LDMOS. A novel test technique using a noise-reduction scheme to test HV-LDMOS is presented in this paper. Test simulations were performed on a MOSFET driver IC with a 700 V LDMOS and experimental validation was performed by building a prototype test setup and making hardware measurements for breakdown and leakage tests. This test technique overcomes the test challenges pertaining to power supply and tester system noise, and provides a superior signal-to-noise ratio (SNR) when compared to conventional test methods. The noise-reduction scheme is inexpensive and highly accurate. The fault-model based test approach reduces the test suite for HV-LDMOS to a couple of test measurements which reduces the overall test cost and time.

Nonlinear modeling of LDMOS transistors for high‐power FM transmitters

SUMMARYIn this paper, a nonlinear model of a commercial 10‐W laterally diffused metal oxide semiconductor (LDMOS) transistor for FM transmitters is identified. It is based on high‐frequency small‐signal measurements for the identification of both the parasitic network and the strictly nonlinear dynamic effects, whereas low‐frequency large‐signal measurements are exploited for the description of the dynamic I/V characteristics of the device above the cut‐off of low‐frequency dispersion. A validation of the proposed model is provided by using time‐domain nonlinear measurements carried out at 40 MHz and 100 MHz. Copyright © 2013 John Wiley & Sons, Ltd.

A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

A novel U-shape buried oxide lateral double diffused metal oxide semiconductor (LDMOS) is reported in this paper. The proposed structure features ionized charges in both sides of dielectric between source and gate region to enhance the breakdown voltage. The dielectric between drain and drift region affects on the breakdown voltage by adding a new peak in the electric field profile. Two dimensional simulation with a commercial software tool predicts significantly improved performance of the proposed device as compared to conventional LDMOS structures.

Lead zirconate titanate behaviors in an LDMOS

The behaviors of lead zirconate titanate (PZT) deposited as the dielectric for high-voltage devices are investigated experimentally and theoretically. The devices demonstrate not only high breakdown voltages above 350 V, but also excellent memory behaviors. A drain current—gate voltage (ID—VG) memory window of about 2.2 V is obtained at the sweep voltages of ±10 V for the 350-V laterally diffused metal oxide semiconductor (LDMOS). The retention time of about 270 s is recorded for the LDMOS through a controlled ID—VG measurement. The LDMOS with memory behaviors has potential to be applied in future power conversion circuits to boost the performance of the energy conversion system.

3-D Multilayer Copper Interconnects for High-Performance Monolithic Devices and Passives

This paper presents a new and efficient low-cost multilayer 3-D copper interconnect process for monolithic devices and passives. It relies on the BPN and SU-8 photoresists, associated with an optimized electroplating process to form multilevel 3-D interconnects in a single metallization step. The SU-8 is used as a permanent thick dielectric layer that is patterned underneath specific locations to create the desired 3-D interconnect shape. A 3-D seed layer is deposited above the SU-8 and the substrate to ensure 3-D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized 3-D copper electroplating process is later used to grow 3-D interconnects, ensuring transition between all metallic layers. Finally, high-Q (55 at 5 GHz) power inductors are designed and integrated above a 50 W RF power laterally diffused metal oxide semiconductor device using this process.

Investigation of class J continuous mode for high‐power solid‐state RF amplifier

The class J design space is investigated with half wave current excitation for a solid-state RF amplifier capable of delivering hundreds of watts. Unlike conventional class J designs, the present analysis aims to explore a continuous design space in order to operate a commercially available device, within its practical limits of drain voltage. This design analysis together with package effects and the inclusion of non-linear capacitor is verified experimentally by fabricating a high-power (550 W CW) high-efficiency (62.8%) solid-state amplifier operating at 505.8 MHz. This power was obtained by in-phase combining two similar continuous class J stages, each one contributing half of the total power. For high-power lateral diffused metal-oxide semiconductor devices, the class J design space is found to be more realisable than popular modes of operation in view of the large non-linear output capacitance of the device. The measured output power, efficiency, spurious response and large signal output reflection coefficients are satisfactory and as anticipated from the design analysis. Since the final application of this amplifier is for a solid-state transmitter, a study of repeatability in terms of phase and amplitude imbalances was carried out by fabricating and evaluating multiple amplifiers, each one working with the proposed design principle.

Improving Breakdown Voltage of LDMOS Using a Novel Cost Effective Design

A reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device with the concept of charge compensation using p-implant layer (PIL) without additional process step is proposed in standard 0.18-μm technology. By simply using the p-type drift drain (PDD) implantation of p-type LDMOS into n-type LDMOS, breakdown voltage (VBD) is substantially improved. For a thorough study of device phenomena, hydrodynamic transport simulations are first performed to analyze the electric field distributions at high voltage bias in order to explain increases in breakdown voltage and predict its optimal design parameter. Then fabrication of the devices is performed and shows that the breakdown voltages increase significantly. The measurement results show a 12% improvement in VBD and a 5% improvement in figure of merit (FOM). Throughout the fabrication process, the enlarged breakdown voltage obtained by the PIL without additional process and device area show the potential of cost effective. Because such devices have good off-state breakdown voltage and specific on-resistance, they are very competitive with similar technologies and promising system-on-chip (SOC) applications.

A dc model for partially depleted SOI laterally diffused MOSFETs utilizing the HiSIM-HV compact model

This paper presents a subcircuit compact model to study the dc characteristics of a partially depleted (PD) SOI laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) utilizing the HiSIM-HV compact model. Our model accounts both for the high-voltage and the floating-body effects such as the quasi saturation effect, the impact ionization in the drift region and the famous kink effect. The high-voltage effects, due to the surface MOS region of PD SOI LDMOSFET, are modeled using the HiSIM-HV model. The HiSIM-HV model, a surface-potential-based compact model, is used as a baseline model as it determines the potential consistently in the complete PD SOI LDMOSFET. And, to incorporate the floating-body effects into the HiSIM-HV model, we have used the same approach as used in developing BSIMSOI model. It is shown that to model the floating-body effects, mainly the kink in the output characteristics, the current due to the impact ionization in the drift region (I KIRK ) needs to be accurately modeled. An external current controlled current source (CCCS) is included in the proposed subcircuit model to model I KIRK accurately. The model is validated for a set of channel and drift lengths to demonstrate the scalability of the model. The accuracy of the proposed subcircuit model is verified using 2-D numerical simulations.

Voltage dependences of parameter drifts in hot carrier degradation for n-channel LDMOS transistors

• We evaluate the hot carrier degradation mechanisms for n-channel LDMOS transistor with STI based structures. • The slope of I D,lin degradation indicates the different degradation mechanism under various bias stress. • The location of peak impact ionization differs at various V GS stress but consistent at various V DS stress. • The degradation mechanism is highly dependent on the stress voltage at the gate ( V GS ). • The V DS is found as an accelerating factor for the hot carrier stress test. The reliability characterization in shallow trench isolation (STI) based n-channel lateral diffused metal–oxide–semiconductor (LDMOS) transistor has recently drawn much attention. A thorough investigation of the hot carrier degradation under various gate and drain stress biases are carried out to gain an insight on the bias dependences of the parameter drifts. The findings are supported by both experimental and the technology computer-aided design (TCAD) simulations data. Based on the results, the drain voltage ( V DS ) parameter was found as a significant accelerating factor for the test. The analysis of HCI damage phenomenon on this device shows that the degradation mechanism is highly dependent on the stress voltage at the gate ( V GS ).

Characteristics of Lateral Diffused Metal–Oxide–Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide

Characteristics of lateral diffused metal–oxide–semiconductor (LDMOS) transistors with gradual junction profile by self-alignment implant through dual thicknesses of screen oxide are presented in this letter. Compared with LDMOS transistors with traditional junction profile, this new device shows improved off-state breakdown voltage, less severe in Kirk effect, and wider electrical safe operating area; without sacrificing device drivability. Technology computer aided design (TCAD) simulation results reveal that this new device has smaller electric field both in off- and on-state bias conditions. Hot-carrier induced degradation of this new device under various stress conditions is also investigated and compared with that of the device with traditional junction profile.

Thermal Conductivity of SOI LDMOS Device

In this paper, the thermal conductivity of lateral double diffused metal oxide semiconductor (LDMOS) was studied. In order to optimize their properties, the LDMOS device based on the lower surface of field (RESURF) theory join the second field plate technology. Power device self-heating effect will affect the carrier mobility, making its negative resistance effect in IV characteristic curve under the high-power condition. As the thermal conductivity of SiO2 is low, the self-heating effect of SOI device is more obvious. The simulation using Silvaco -TCAD software for different buried oxide (BOX) with different SOI layer thickness accordingly show that the thicker SOI layer and the thinner buried oxide layer, the smaller the self-heating effect.

Modelling of LDMOS transistor using artificial neural networks: DC and RF performances

This article presents an accurate method based on artificial neural networks (ANNs) for DC and RF modelling of laterally diffused metal oxide semiconductor (LDMOS) transistors, under various temperature conditions. In LDMOS transistors, temperature is an effective factor, so the proposed models include this parameter. Two neural networks‐based procedures have been proposed for LDMOS transistor modelling, first for DC and second for RF modelling. In each case, two kinds of neural networks have been used, multilayer perceptron and radial basis function neural networks. Two models are compared to each other in terms of accuracy, and for both of them, an excellent agreement between modelled and measured data is obtained. The ANN model is developed and trained with the help of data obtained by simulation of a Si‐LDMOS transistor using ADS software.

A Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltage

In this work, double reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device combines a new implant technology without using additional mask in standard 0.18 µm technology has been proposed and successfully fabricated. The breakdown voltage (BV) can be improved significantly with simply changing the implanted region length in this implant technology. Firstly, hydrodynamic transport simulations which analyze the high bias condition electric field distributions are examined to predict and explain the increase of breakdown voltage. Then the fabricated devices process flow is demonstrated, the structures are performed, and the breakdown voltages increase with different n-type double diffusion (NDD) photoresistor (PR) size using the change of PR exposure dose are investigated. The measurement results show that maximum NDD PR size achieves BV improvement of 6.3%, and 5% increase of figure of merit (FOM) evaluation. Throughout the whole fabrication process, no additional mask and device area show the potential of cost effective with the proposed technique. Such devices with good off-state breakdown voltage and specific on-resistance are very competitive with similar technologies and show good promising in system on chip (SOC) applications.