Dielectric Breakdown Measurements Research Articles

Effect of silane coupling agent chemistry on electrical breakdown across hybrid organic-inorganic insulating films.

Dielectric breakdown measurements were conducted on self-assembled monolayer (SAM)/native silicon oxide hybrid dielectrics using conductive atomic force microscopy (C-AFM). By depositing silane coupling agents (SCAs) through a diffusional barrier layer, SAM roughness was decoupled from chemistry to compare the chemical effects of exposed R-group functionality on dielectric breakdown. Using Weibull and current-voltage (I-V) analysis, the breakdown strength was observed to be independent of SCA R-group length, and the addition of a SAM was seen to improve the breakdown strength relative to native silicon oxide by up to 158%. Fluorinated SCAs were observed to suppress tunneling leakage and exhibited increased breakdown strength relative to their hydrocarbon analogs. Electron trapping, scattering, or attachment processes inherent to the fluorinated moieties are thought to be the origin of the improved breakdown properties.

Multiple breakdown model of carpet-bombing-like concaves formed during dielectric breakdown of silicon carbide metal–oxide–semiconductor capacitors

We observed characteristic “carpet-bombing-like concaves” after time-to-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) measurement for silicon carbide metal–oxide–semiconductor capacitors with a thermally grown oxide. A multiple breakdown model is proposed to explain the formation mechanism of the carpet-bombing-like concaves in TZDB measurement. Results and analysis of our TDDB measurements consistently support our multiple breakdown model.

Characterization of scraper-shaped defects on 4H-SiC epitaxial film surfaces

We have found undiscovered defects on a 4H-SiC epitaxial layer, the shape of which resembles a scraper in images taken by confocal differential interference contrast optical microscopy. The surface morphological structure and formation mechanism of the scraper-shaped defects were investigated by atomic force microscopy and grazing incidence monochromatic synchrotron X-ray topography, respectively. The scraper-shaped defects were surface morphological defects consisting of surface asperity and were caused by the migration of interfacial dislocations. The evaluation of the thermal oxide reliability of metal–oxide–semiconductor capacitors fabricated on these defects was performed by time-dependent dielectric breakdown measurement. The degradation of thermal oxide occurred only on the downstream line of the scraper-shaped defects. The thickness of the oxide layer on these defects was also investigated using cross-sectional transmission electron microscopy.

Electrical Properties of Nano Aluminum-Polymer Composite

Conducting polymers have attracted a large amount of attention since 1970 for being lightweight, flexible, durable alternatives to current conducting systems. When certain conditions are met, insulating polymers can be made to conduct electricity with the addition of electrically conductive nanoparticles. The factors that influence a polymer composite’s conductivity include the concentration, size and inter-particle spacing between conducting nanoparticles. Metal nanoparticles are also well known for the enhanced conductive and optical properties compared to their bulk material counterparts. Metal nanoparticle-polymer composites show promise of great thermal, electrical and optical properties with potential applications as biosensors, electronics, thin film solar cells and other areas. Work was done to form a composite of polymer and aluminum nanoparticles to form a conducting polymer. With a synthesis process that allows precise control of particle size, concentration and dispersion of particles within a polymer solution, we are able to tailor thin film structures and measure electrical properties. Characterization of this material included electrical measurements such resistivity at different temperatures, dielectric relaxation spectroscopy, dielectric breakdown measurements, and impedance spectroscopy.

Gate oxide reliability on trapezoid-shaped defects and obtuse triangular defects in 4H-SiC epitaxial wafers

The reliability of the gate oxide on large-area surface defects (trapezoid-shaped and obtuse triangular defects) in 4H-SiC epitaxial wafers is discussed. Time-dependent dielectric breakdown measurements revealed that a reduction in charge-to-breakdown (Qbd) occurred at a MOS capacitor including the downstream line of those defects. The deterioration of Qbd was at the same level in trapezoid-shaped defects and obtuse triangular defects. A cross-sectional transmission electron microscope (TEM) image and the simulation of the electric field distribution for the MOS structure indicated that the local fluctuation of the oxide thickness and/or the roughness of the interface on the downstream lines caused the degradation of the reliability of the MOS capacitors.

Correlation between Structure and Dielectric Breakdown in LDPE/HDPE/Clay Nanocomposites

Cross-linked polyethylene (XLPE) is commonly used in medium/high voltage insulation due to its excellent dielectric properties and acceptable thermomechanical properties. To improve both electrical and thermal properties to a point that would possibly avoid the need for crosslinking, nanoclay fillers can be added to polymer matrix to form nanocomposites materials. In this paper, PE/clay nanocomposites were processed by mixing a commercially available premixed polyethylene/O-MMT masterbatch into a polyethylene blend matrix containing 80 wt% low density polyethylene LDPE and 20 wt% high density polyethylene HDPE with and without compatibilizer using a corotating twin-screw extruder. Various characterization techniques were employed in this paper, including optical microscopy, AFM, TEM, TGA, DMTA, and dielectric breakdown measurements in order to understand the correlation between structure and short-term dielectric breakdown strength.

Reliability of CMOS on Silicon-on-Insulator for Use at 250 $^{\circ}\hbox{C}$

This paper deals with the reliability of a 1.0- μm CMOS-silicon-on-insulator (SOI) process, which is intended for use at 250 °C. The goal is to give an overview of the most important reliability aspects that concern devices and circuits at temperatures of 250 °C and above. The investigated reliability aspects are the gate oxide integrity in terms of time-dependent dielectric breakdown measurements, electro- and stress migration, and the EEPROM reliability such as the data retention and the endurance, as well as transistor aspects (e.g., hot carrier, negative bias temperature instability) and the long-term stability of a ring oscillator and a band-gap reference. As most of the commonly applied methods for accelerated reliability testing and analysis are not designed to be used at such high temperatures, this paper evaluates in which way the known models can be applied and which physical mechanisms have to be considered. Since temperatures of 250 °C and more are necessary for testing, the investigations also yield an estimate of the temperature limit of use for CMOS on SOI. The results indicate that the use of CMOS on SOI is, in principle, possible up to 400 °C.

Step-Bunching Dependence of the Lifetime of MOS Capacitor on 4<sup>o</sup> Off-Axis Si-Face 4H-SiC Epitaxial Wafers

The step-bunching dependence of the lifetime of metal–oxide–semiconductor capacitors on 4° off-axis 4H-SiC epitaxial wafers was investigated. The effects of the C/Si ratios in epitaxial growth and the substrate properties were examined. Step-bunching was observed at the base of triangle or trapezoid defects. Step-bunching decreased as the C/Si ratio was reduced. Time-dependent dielectric breakdown (TDDB) measurements showed that the locations of short lifetime breakdowns closely matched step-bunching positions. TDDB measurements of four different commercial substrates showed clear differences in capacitor lifetime.

Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

New approach to evaluate area-dependent breakdown characteristics of dielectric polymer films

A new dielectric breakdown measurement method for determining breakdown characteristics of polymer films has been developed and evaluated. The method is based on measurement of multiple breakdowns per sample area beyond the weakest point of the film by utilizing low-energy self-healing breakdown of metallized polymer film. A data selection process based on the discharge energy characteristics of each measured self-healing breakdown is utilized prior to the statistical analysis in order to validate the mutual independence of the results. Even with a relatively small sample area, the method yields a large amount of breakdown data from a wide voltage spectrum, thus enabling the formation of detailed material-specific breakdown fingerprints. The measurement system and the area dependence of the breakdown results have been evaluated with capacitor-grade metallized film. For the statistical analysis, additively mixed Weibull distributions are utilized as multiple breakdown mechanisms are found to be operative in the dielectric. Defects in the dielectric volume are found to have a profound effect on the structure of the mixed distribution with increasing area.

High performance floating‐gate technology compatible antifuse

An antifuse structure that is fully compatible with the standard floating-gate technology is presented. The antifuse consists of an oxide-nitride-oxide dielectric layer, sandwiched between polysilicon and N-well layers. The characteristics of the antifuse are investigated. The off-state resistance of the antifuse is larger than 10 GΩ. The programmed antifuses show linear ohmic characteristics and have a tight resistance distribution centred around 350 Ω. The time dependent dielectric breakdown measurements show that the extrapolated lifetime of the unprogrammed antifuse at 5.5 V is as long as 40 years, and the resistance change of post-program antifuses under the continuous reading mode test is lower than 5%.

Reliability Evaluation of Al2O3 Deposited by Ozone-Based Atomic Layer Deposition on Dry-Etched n-Type GaN

The time-to-breakdown (tBD) of Al2O3 deposited by ozone-based atomic layer deposition (ALD) on dry-etched n-type GaN was evaluated by constant-voltage-stress time-dependent dielectric breakdown (TDDB) measurements. The influence of dry etching was not observed in the TDDB and current–voltage (I–V) measurements at room temperature. The tBD of the ALD-Al2O3 film was estimated to be more than 40,000 years at 3 MV/cm and room temperature. However, the tBD estimated at 250 °C was around 102–103 s.

Relation between Defects on 4H-SiC Epitaxial Surface and Gate Oxide Reliability

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Reliability of $\hbox{SrRuO}_{3}\hbox{/SrTiO}_{3}\hbox{/SrRuO}_{3}$ Stacks for DRAM Applications

A layer stack of strontium ruthenate/strontium titanate/strontium ruthenate was fabricated by low-rate rf sputtering. A high dielectric permittivity of approximately 200 at a capacitive effective thickness of 0.4 nm in combination with a very low leakage current density JC of 5 × 10-9 A/cm2 at 833 kV/cm was achieved. JC is characterized by a Curie-von Schweidler law before current degradation, and stress-induced leakage current sets in. The charge loss due to dielectric absorption showed values below 2% and was evaluated by a transient floating potential setup. From time-dependent dielectric breakdown measurements, we extrapolated an operating lifetime of approximately 7.5 years.

(Invited) Voltage Ramp Stress Based Stress-And-Sense Test Method For Reliability Characterization of Hf-Base High-k/Metal Gate Stacks For CMOS Technologies

Traditionally, the reliability of gate oxides is mostly evaluated using a Constant Voltage Stress, CVS, based stress-and-sense methodology, in which a constant stress voltage is interrupted to quantify the degradation. In this paper, we discuss the use of a Voltage-Ramp Stress, VRS, based stress-and-sense method in which the stress voltage is ramped at a constant rate and degradation is quantified by interrupting the VRS at increasingly higher stress voltages. The two methods are used and compared for dielectric breakdown and bias temperature instability measurements using high-k/metal gate stacks. It is shown that the two methods can be used interchangeably, producing very similar reliability assessments. It is shown that the VRS method, however, has distinct advantages over a CVS approach. It is fast and 'foolproof', providing reliable information on the voltage acceleration without any prior knowledge on the dynamics of the degradation. The use of a VRS is therefore well suited for monitoring reliability parameters during gate stack and process development, and during device optimization, where large variations in the reliability parameters are common.

Advanced Organic Polymer for the Aggressive Scaling of Low-k Materials

An advanced organic polymer material of k = 2.2 has been successfully integrated in Cu lines with dielectric spacing from 80 to 20 nm. Cu lines with both TaN/Ta barrier and no barrier were fabricated. Current–voltage (I–V) and time dependent dielectric breakdown (TDDB) measurements were performed to study the scalability of this material. In the case of TaN/Ta barrier, no TDDB degradation was observed at 100 °C as the dielectric spacing changed from 80 to 30 nm. In the case of no barrier, TDDB performance at 100 °C was better than that of SiO2 without a barrier. However, TDDB at 200 °C showed a clear degradation. In contrast, no such degradation was present when TaN/Ta barrier was used.

SiON and SiO 2/HfSiON gate oxides time dependent dielectric breakdown measurements at nanoscale in ultra high vacuum

Time dependent dielectric breakdown (TDDB) measurements on a nano-scale using an AFM tip under ultra high vacuum as upper electrode are systematically compared to device measurements in this paper. Both studies were performed on the same SiON or SiO 2/HfSiON gate oxides. The shape factor of the TDDB distribution and the acceleration factor are compared at both scales.

TDDB and Pulse-Breakdown Studies of Si-Rich $ \hbox{SiN}_{x}$ Antifuses and Antifuse-Based ROMs

Antifuses are electronic devices that can be irreversibly converted from a high-resistance state to a low-resistance state. Thus, they are ideal candidates for one-time-programmable many-times-readable nonvolatile memories. In this paper, the reliability and the programming characteristics of Si-rich SiNx, antifuses have been studied using time-dependent dielectric breakdown and pulse-breakdown measurements on both single-device test structures and full read-only memories. Contrary to measurements on thick films in which the Poole-Frenkel barrier lowering dominates breakdown, these measurements on fully processed and integrated antifuses indicate that a Fowler-Nordheim-like mechanism governs both programming and long-term reliability.

Physical properties of epoxy resin/titanium dioxide nanocomposites

AbstractA polymeric nanocomposite system (nanodielectric) was fabricated, and its mechanical properties were determined. The fabricated nanocomposite was composed of low concentrations of monodispersed titanium dioxide (TiO2) nanoparticles and an epoxy resin specially designed for cryogenic applications. The monodispersed TiO2 nanoparticles were synthesized in an aqueous solution of titanium chloride and polyethylene glycol and subsequently dispersed in a commercial‐grade epoxy resin (Araldite® 5808). Nanocomposite thin sheets were prepared at several weight fractions of TiO2. The morphology of the composites, determined by transmission electron microscopy, showed that the nanoparticles aggregated to form particle clusters. The influence of thermal processing and the effect of filler dispersion on the structure–property relationships were identified by differential scanning calorimetry and dynamic mechanical analysis at a broad range of temperatures. The effect of the aggregates on the electrical insulation properties was determined by dielectric breakdown measurements. The optical properties of the nanocomposites and their potential use as filters in the ultraviolet–visible (UV–vis) range were determined by UV–vis spectroscopy. POLYM. ENG. SCI., 2011. © 2010 Society of Plastics Engineers