Field Programmable Gate Array Design Research Articles

A Compact FPGA‐Based Accelerator for Curve‐Based Cryptography in Wireless Sensor Networks

The main topic of this paper is low‐cost public key cryptography in wireless sensor nodes. Security in embedded systems, for example, in sensor nodes based on field programmable gate array (FPGA), demands low cost but still efficient solutions. Sensor nodes are key elements in the Internet of Things paradigm, and their security is a crucial requirement for critical applications in sectors such as military, health, and industry. To address these security requirements under the restrictions imposed by the available computing resources of sensor nodes, this paper presents a low‐area FPGA‐prototyped hardware accelerator for scalar multiplication, the most costly operation in elliptic curve cryptography (ECC). This cryptoengine is provided as an enabler of robust cryptography for security services in the IoT, such as confidentiality and authentication. The compact property in the proposed hardware design is achieved by implementing a novel digit‐by‐digit computing approach applied at the finite field and curve level algorithms, in addition to hardware reusing, the use of embedded memory blocks in modern FPGAs, and a simpler control logic. Our hardware design targets elliptic curves defined over binary fields generated by trinomials, uses fewer area resources than other FPGA approaches, and is faster than software counterparts. Our ECC hardware accelerator was validated under a hardware/software codesign of the Diffie‐Hellman key exchange protocol (ECDH) deployed in the IoT MicroZed FPGA board. For a scalar multiplication in the sect233 curve, our design requires 1170 FPGA slices and completes the computation in 128820 clock cycles (at 135.31 MHz), with an efficiency of 0.209 kbps/slice. In the codesign, the ECDH protocol is executed in 4.1 ms, 17 times faster than a MIRACL software implementation running on the embedded processor Cortex A9 in the MicroZed. The FPGA‐based accelerator for binary ECC presented in this work is the one with the least amount of hardware resources compared to other FPGA designs in the literature.

A New 4-D Multi-Stable Hyperchaotic System With No Balance Point: Bifurcation Analysis, Circuit Simulation, FPGA Realization and Image Cryptosystem

In this work, we describe the model of a new 4-D hyperchaotic system with no balance point and deduce that the new hyperchaotic system has a hidden attractor. We present a detailed bifurcation analysis for the new hyperchaotic dynamo system with respect to the system parameters and also exhibit that the new hyperchaotic system displays multistability with coexisting attractors. Using NI Multisim 14.0, we design an electronic circuit for the implementation of the new 4-D hyperchaotic system and present the circuit simulation results. We also show the implementation of the new 4-D hyperchaotic system by using a field programmable gate array (FPGA). The hardware resources are reduced by designing single-constant multipliers, adders, subtractors and multipliers. The FPGA design is done for three numerical methods, namely: Forward-Euler, Backward-Euler and fourth-order Runge-Kutta. We demonstrate that experimental chaotic attractors are in good agreement with theoretical simulations. To verify the ability of the presented hyperchaotic system for designing robust cryptosystems, we suggest a novel image cryptosystem using the proposed hyperchaotic system. Simulation outcomes confirm the effectiveness of the proposed image cryptosystem, and consequently, the effectiveness of the proposed 4-D hyperchaotic system in designing diverse cryptographic purposes.

A Deep Learning-Based FPGA Function Block Detection Method With Bitstream to Image Transformation

In the context of various application scenarios and/or for the sake of strengthening field-programmable gate array (FPGA) security, the system functions of an FPGA design need to be analyzed, which can be achieved by systematically partitioning the FPGA's bitstream into manageable functional blocks and detecting their functionalities thereafter. In this paper, we propose a novel deep learning-based FPGA function block detection method with three major steps. In specific, we first analyze the format of the bitstream to obtain the mapping relationship between the configuration bits and configurable logic blocks because of the discontinuity of the configuration bits in the bitstream for one element. In order to reap the maturity of object detection techniques based on deep learning, our next step is to convert an FPGA bitstream to an image, following the proposed transformation method that takes account of both the adjacency nature of the programmable logic and the high degree of redundancy of configuration information. Once the image is obtained, a deep learning-based object detection algorithm is applied to this transformed image, and the objects detected can be reflected back to determine the function blocks of the original FPGA design. The deep neural network used for function block detection is trained and validated with a specially crafted bitstream/image dataset. Experiments have confirmed high detection accuracy of the proposed function detection method, showing a 98.11% of mean Average Precision (IoU=0.5) for 10 function blocks within a YOLOv3 detector implemented on Xilinx Zynq-7000 SoCs and Zynq UltraScale+ MPSoCs.

FPGA-Based Wigner–Hough Transform System for Detection and Parameter Extraction of LPI Radar LFMCW Signals

Low probability of intercept (LPI) radars using linear frequency-modulated continuous waveforms (LFMCWs) is rapidly proliferating in the military domain and posing a serious challenge to conventional electronic support receivers (ESRs). In this article, we provide a practical approach that can be used in digital ESR systems for real-time LFMCW radar signal detection and parameter extraction under challenging SNR levels. We proposed a modified version of the Wigner–Ville distribution (WVD), namely, short-time Wigner distribution (STWD), postprocessing steps, e.g., column-based thresholding of STWD combined with the Hough transform (HT), and a field-programmable gate array (FPGA) design as an embedded solution with low computational complexity. The performance of the proposed system is tested with MATLAB and hardware simulations using a signal database generated with different signal-to-noise ratio (SNR) levels. The system is then embedded into a Virtex-7 FPGA where the performance evaluations showed satisfactory detection results down to −6-dB SNR level, and parameter extraction results down to −8-dB SNR level.

Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks

The advent of space applications with increased computational requirements has led the space industry to consider innovative chips and avionics architectures for high-performance on-board data processing. In a relatively limited market, the European BRAVE family of Field-Programmable Gate Arrays (FPGAs) offers such novel radiation-hardened solutions. Towards verification, the current work devises and applies a methodology to thoroughly assess the BRAVE FPGAs and their SW tools. The paper focuses on NG-Large, i.e., the largest FPGA of the 65nm Radiation-Hardened-By-Design (RHBD) technology of NanoXplore to date. The proposed approach comprises a number of customized steps to systematically evaluate the entire FPGA design flow. Initially, we carefully select and tune a set of high-performance Digital Signal Processing (DSP) & Computer Vision (CV) benchmarks, which were originally developed as Hardware Description Language (HDL) IPs in past projects of the European Space Agency (ESA). Subsequently, we perform exhaustive exploration of the Synthesis, Placement, and Routing stages of the SW tools, as well as testing on actual HW boards. At each step, we generate and analyze a variety of results, while we also compare them to 3rd-party solutions. The results show that NG-Large provides sufficient programmability and performance, e.g., classic CV IPs for feature detection on megapixel images can achieve a throughput of 5–10 frames per second, while the on-chip memory utilization is up to 56% better than that of 3rd-party FPGAs. As a highlight, at system-level, we successfully implement and execute an entire HW/SW algorithmic pipeline for Vision-Based Navigation (VBN) involving SpaceWire data transfers with LEON CPU & NG-Large co-processing.

An easy to implement logic analyzer for long-term precise measurements

Most of market-available logic analyzers are designed for hardware debug purposes and cannot record continuous measurement in long-term while in different fields of scientific research it is necessary to make data acquisition within small periods (less then 1 ms) during several hours or even days. The common example is real-time communication worst-case jitter analysis. This paper introduces an easy to implement approach how to create a logic analyzer for such kind of task on a basis of a low-cost Field-Programmable Gate Array (FPGA) kit and a personal computer. The Author provides both sample FPGA design files compatible with an open-source toolchain and the approach how to collect data using standard software and Octave scripts to post-process the experimental result. Following the Author’s guidelines even with minimal knowledge in FPGA design makes it easy to modify the introduced hardware for specific laboratory team needs.

High-Resolution Time-to-Digital Converters Implemented on 40-, 28-, and 20-nm FPGAs

This work proposed the implementations of high-resolution time-to-digital converters (TDCs) on field-programmable gate array (FPGA) platforms with different manufacturing technologies: 40-nm Virtex-6, 28-nm Kintex-7, and 20-nm Kintex UltraScale. The large-scale multiphase matrix (LSPM) structure is employed, which is different from the commonly used delay line structure. Experimental results have proved that all the three implementations have achieved competitive resolution. In particular, the Kintex-7 LSPM-TDC has achieved a resolution of 1.29 ps, ranking among the best performing FPGA-based TDCs. The dynamic ranges of the Virtex-6, Kintex-7, and Kintex UltraScale TDCs are 22, 11, and 18 s, respectively. The LSPM-TDCs implemented on Virtex-6, Kintex-7, and Kintex UltraScale have demonstrated equivalent dynamic range as the state-of-the-art FPGA-based TDCs, but without using the “two-stage” method that worsens the precision. Moreover, experiment and comparison between implementations with different manufacturing technologies are provided. With the technology advances from 65 to 28 nm, steady improvements in resolution are acquired. However, the 20-nm Kintex UltraScale performs not as good as the 28-nm Kintex-7. Experimental results also demonstrate that the phase noise and dynamic power consumption are reduced in platforms with more advanced technology. The discussion of routing delay and jitter of the reference clock provides a reference for FPGA designs.

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

This paper presents a methodology for the design of field-programmable gate array (FPGA)-based real-time simulators (RTSs) for power electronic circuits (PECs). The programmability of the simulator results from the use of an efficient and scalable overlay architecture (OA). The proposed OA relies on a latency-insensitive design (LID) paradigm. LID consists of connecting small processing units that automatically synchronize and exchange data when appropriate. The use of such data-driven architecture aims to ease the design process while achieving a higher computational efficiency. The benefits of the proposed approach is evaluated by assessing the performance of the proposed solver in the simulation of a two-stage AC–AC power converter. The minimum achievable time-step and FPGA resource consumption for a wide range of power converter sizes is also evaluated. The proposed overlays are parametrizable in size, they are cost-effective, they provide sub-microsecond time-steps, and they offer a high computational performance with a reported peak performance of 300 GFLOPS.

WITHDRAWN: Upgrade of service industry structure based on FPGA and machine learning

Abstract The service industry gradually exceeds the manufacturing industry structure has become the largest sector of the which is also the efforts of pillar However, this view has been stepped up to develop a growing this popular view, mainly based on the traditional economic thinking on the industrial In the context of the global industrial integration of today, some of the opinions are the question. Whether it is replaced by the service industry, the US strategy of a show has played an essential role in the national economy re-industrialization. Dynamic Stochastic General Equilibrium (DSGE) models of the manufacturing and service industry are constituted in this chapter, integrating the two sectors to analyze the influence of economic, industrial structure transformation. Numerical simulation, while does not change the innovative impact of the service industry is less, of potential for economic growth in the contribution of the service industry to the cause GDP growth rate, in terms of, of the manufacturing industry innovation, it shows that will affect the growth of GDP. In the service industry, but is the stabilization of the economy, outside of the technological progress in the overall economic system, it is weaker than that of the manufacturing industry. The balance must be achieved in the manufacturing and service industries in the future development process of upgrading of industrial structure. Field-programmable gate array (FPGA) design methodology of this field is focused on the status of the application program of industrial control systems. In this article, the design approach, using the programming/design tools of development tools and portable hardware description languages and system level, followed by the related environment, including the beginning of the presentation, use an overview of the development of the FPGA technology.

FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction

This article proposes an improved orthogonal matching pursuit (OMP) algorithm and its implementation with Xilinx Vivado high-level synthesis (HLS). We use the Gram–Schmidt orthogonalization to improve the update process of signal residuals so that the signal recovery only needs to perform the least-squares solution once, which greatly reduces the number of matrix operations in a hardware implementation. Simulation results show that our OMP algorithm has the same signal reconstruction accuracy as the original OMP algorithm. Our approach provides a fast and reconfigurable implementation for different signal sizes, different measurement matrix sizes, and different sparsity levels. The proposed design can recover a 128-length signal with measurement number $M=32$ and sparsity $K=5$ and $K=8$ in 13.2 and $21~\mu \text{s}$ , which is at least a 21.9% and 22.2% improvement compared with the existing HLS-based works; a 256-length signal with $M=64$ and $K=8$ in $20.6~\mu \text{s}$ , which is a 24% improvement compared with the existing work; and a 1024-length signal with measurement number $M=256$ and sparsity $K=12$ and $K=36$ in 150.3 and $423~\mu \text{s}$ , respectively, which are close to the results of traditional hardware description language (HDL) implementations. Our results show that our improved OMP algorithm not only offers a superior reconstruction time compared with other recent HLS-based works but also can compete with existing works that are implemented using the traditional field-programmable gate array (FPGA) design route.

PRACTICAL ASPECTS OF OPERATING AND ANALYTICAL RELIABILITY ASSESSMENT OF FPGA-BASED I&C SYSTEMS

Operating reliability assessment of instrumentation and control systems (I&Cs) is always one of the most important activities, especially for critical domains such as nuclear power plants (NPPs). It is an important source of I&C reliability information preferable to lab testing data because it provides information on I&C reliability under real use conditions. That is the reason that now it is a common practice for companies to have an established process of collecting operating reliability data on a large variety of used components on regular basis, maintaining a database with failure information, total operation time, typical failure modes, etc. The intensive use of complicated components like field-programmable gate arrays (FPGAs) in I&C which appear in upgrades and newly-built nuclear power plants makes the task to develop and validate advanced operating reliability assessment methods that consider specific technology features very topical. Increased integration densities make the reliability of integrated circuits the most crucial point in modern NPP I&Cs. Moreover, FPGAs differ in some significant ways from other integrated circuits: they are shipped as blanks and are very dependent on the design configured into them. Furthermore, FPGA design could be changed during planned NPP outage for different reasons. Considering all possible failure modes of FPGA-based NPP instrumentation and control systems at the design stage is a quite challenging task. Therefore, operating reliability assessment is one of the most preferable ways to perform a comprehensive analysis of FPGA-based NPP I&Cs. Based on information in the literature and own experience, operational vs analytical reliability could be pretty far apart. For that reason, analytical reliability assessment using reliability block diagrams (RBD), failure modes, effects and diagnostics analysis (FMEDA), fault tree analysis (FTA), fault insertion testing (FIT), and other techniques and their combinations are important to meet requirements for such systems. The paper summarizes our experience in operating and analytical reliability assessment of FPGA based NPP I&Cs.

MEM-OPT: A Scheduling and Data Re-Use System to Optimize On-Chip Memory Usage for CNNs On-Board FPGAs

In the last years, Convolutional Neural networks (CNNs) found applications in many fields from computer vision to speech recognition, showing outstanding results in terms of accuracy. Field Programmable Gate Arrays (FPGAs) proved to be a promising platform for running CNN algorithms because they offer a remarkable trade-off between power consumption and computational power. However, an efficient implementation of CNN models on-board an FPGA represents a complex task since CNN massive parallel processing is often limited by FPGA storage capabilities and design congestion. This article introduces MEM-OPT, a scheduling algorithm and data re-use system that aims to optimize on-chip memory usage on-board FPGAs for what concerns input feature maps storage and Processing Elements multiply and accumulation process. The work presents MEM-OPT implementations results on a Xilinx XC7Z020, including hardware resources, maximum clock frequency and power consumption. MEM-OPT memory requirements are analyzed for LeNet-5, MobileNet, VGG-16 and other state-of-the-art CNNs, showing, a reduction up to 80% of the overall on-chip memory necessary for storing input feature maps and accumulating output results with respect to alternative solutions available in the literature.

Accelerating Faceting Wide-Field Imaging Algorithm with FPGA for SKA Radio Telescope as a Vast Sensor Array.

The SKA (Square Kilometer Array) radio telescope will become the most sensitive telescope by correlating a huge number of antenna nodes to form a vast array of sensors in a region over one hundred kilometers. Faceting, the wide-field imaging algorithm, is a novel approach towards solving image construction from sensing data where earth surface curves cannot be ignored. However, the traditional processor of cloud computing, even if the most sophisticated supercomputer is used, cannot meet the extremely high computation performance requirement. In this paper, we propose the design and implementation of high-efficiency FPGA (Field Programmable Gate Array) -based hardware acceleration of the key algorithm, faceting in SKA by focusing on phase rotation and gridding, which are the most time-consuming phases in the faceting algorithm. Through the analysis of algorithm behavior and bottleneck, we design and optimize the memory architecture and computing logic of the FPGA-based accelerator. The simulation and tests on FPGA are done to confirm the acceleration result of our design and it is shown that the acceleration performance we achieved on phase rotation is 20× the result of the previous work. We then further designed and optimized an efficient microstructure of loop unrolling and pipeline for the gridding accelerator, and the designed system simulation was done to confirm the performance of our structure. The result shows that the acceleration ratio is 5.48 compared to the result tested on software in gridding parts. Hence, our approach enables efficient acceleration of the faceting algorithm on FPGAs with high performance to meet the computational constraints of SKA as a representative vast sensor array.

ReCoFused partial reconfiguration for secure moving-target countermeasures on FPGAs

Partial reconfiguration is a versatile technique to modify the functionality of field programmable gate arrays (FPGAs) at run time. When performing partial reconfiguration a dedicated intellectual property (IP) component of the FPGA vendor, i.e., the partial reconfiguration controller (PRC), among a wide range of IP components has to be used. While ensuring the functional safety of FPGA designs is well understood, ensuring hardware security still remains challenging. This applies in particular to reconfiguration-based countermeasures which are intensively used to create a moving target for an attacker. Reconfiguration-based countermeasures against side-channel attacks or differential power analysis (DPA) attacks were implemented. However, from the system security perspective, the above mentioned PRC is a critical component as was noticed by many papers before. In this work, we extend a previously proposed safety mechanism which creates a container around an IP, to encapsulate and thereby to protect and observe the PRC of a FPGA. The proposed encapsulation scheme results in an architecture comprising so-called ReCoFuses (RCFs), each capturing a specific protective goal which have to be fulfilled at any time during PRC operation. The terminology follows the classical electric installation including a fuse box. In our scheme we employ formal verification to guarantee the correctness in detecting a security violation. Only after successful verification, the RCFs are integrated into the ReCoFuse Container. Experimental results demonstrate the advantage of our approach by preventing attacks on the PRC of a system secured by partial reconfiguration.

Micro-Infrared Thermopile Detector Space Applications Based on FPGA

Infrared earth sensors are an important attitude measurement component of satellite control subsystems.They provide the information about the satellite’s attitude relative to the pitch and roll direction of the earth radiation disk.The infrared detector is the key part of such a sensor.In this paper,we discuss research on micro-infrared thermopile detectors for space applications.Infrared thermopile technology and the technical index of the detector are introduced.The ring effect,temperature compensation,response compensation,nonuniformity correction,and blind element processing of the detector are studied.The scheme design and field programmable gate array(FPGA)design of an infrared earth sensor image processing system are described.Test results show that system’s attitude measurement deviation is less than 0.2°.Thus,FPGA-based micro-infrared thermopile detectors based on FPGA can be used for attitude measurement in low earth orbit satellites.Offering miniaturization,low power consumption,and low cost,this technology has the potential to replace traditional mechanical scanning infrared earth sensors and has broad application prospects.

Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling

Recent success in applying convolutional neural networks (CNNs) to object detection and classification has sparked great interest in accelerating CNNs using hardware-like field-programmable gate arrays (FPGAs). However, finding an efficient FPGA design for a given CNN model and FPGA board is not trivial since a strong background in hardware design and detailed knowledge of the target board are required. In this work, we try to solve this problem by design space exploration with a collaborative framework. Our framework consists of three main parts: FPGA design generation, coarse-grained modeling, and fine-grained modeling. In the FPGA design generation, we propose a novel data structure, LoopTree, to capture the details of the FPGA design for CNN applications without writing down the source code. Different LoopTrees, which indicate different FPGA designs, are automatically generated in this process. A coarse-grained model will evaluate LoopTrees at the operation level, e.g., add, mult, and so on, so that the most efficient LoopTrees can be selected. A fine-grained model, which is based on the source code, will then refine the selected design in a cycle-accurate manner. A set of comprehensive OpenCL-based designs have been implemented on board to verify our framework. An average estimation error of 8.87% and 4.8% has been observed for our coarse-grained model and fine-grained model, respectively. This is much lower than the prevalent operation-statistics-based estimation, which is obtained according to a predefined formula for specific loop schedules.

FPGA Design of Elliptic Curve Cryptosystem (ECC) for Isomorphic Transformation and EC ElGamal Encryption

Attacking or tampering with sensitive data continues to increase risks to economic processes or human activities. These risks are significant key factors to improve the development and implementation of security systems. Therefore, improving cryptography is essentially needed to enhance the security of critical data. For example, elliptic curve cryptography (ECC) over the Galois field GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">163</sup> ) is one of the public-key (asymmetric) cryptographic techniques, in which demands mapping a message (163-bit) to a point in the prime subgroup of the elliptic curve. To the best of our knowledge, mapping methods are not yet available on Field-Programmable Gate Arrays (FPGAs). Also, asymmetric encryption schemes often do not consider encrypting/decrypting data packets because of their computation complexity and performance limitations. In this letter, we propose and develop a concurrent reconfigurable cryptosystem to encrypt and decrypt stream of data using ECC on FPGA. First, we present hardware design and implementation to map a plain message on the elliptic curve based on isomorphic transformation, then second, we architect the elliptic curve ElGamal public-key encryption method by using point addition and multiplication on Koblitz elliptic curve on FPGA. Our proposed cryptosystem is synthesized and implemented on Intel Cyclone 10 GX and Xilinx Kintex-7 FPGAs to evaluate throughput, and it achieves 25.73-57.1 Mbps.

Two Open Solutions for Industrial Robot Control: The Case of PUMA 560

In this paper we present two different, software and reconfigurable hardware, open architecture approaches to the PUMA 560 robot controller implementation, fully document them and provide the full design specification, software code and hardware description. Such solutions are necessary in today’s robotics and industry: deprecated old control units render robotic installations useless and allow no upgrades, advancements, or innovation in an inherently innovative ecosystem. For the sake of simplicity, just the first robot axis is considered. The first approach described is a PC solution with data acquisition I/O board (Humusoft MF634). This board is supported with Matlab Real-Time Windows Toolbox for real-time applications and thus whole controller was designed in Matlab environment. The second approach is a robot controller developed on field programmable gate arrays (FPGA) board. The complexity of FPGA design can be overcome by using a third party software package, such as self-developed Matlab FPGA Real Time Toolbox. In both cases, parameters of motion controller are calculated by using simulation of the PUMA 560 robot first axis motion. Simulations were conducted in Matlab/Simulink using Robotics Toolbox.

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

This paper addresses the problem of hardware tasks reliability estimation in harsh environments. A novel statistical model is presented to estimate the reliability, the mean time to failure, and the number of errors of hardware tasks running on static random-access memory (SRAM)-based partially run-time reconfigurable field programmable gate arrays (FPGAs) in harsh environments by taking both single-bit upsets and multiple-cell upsets into account. The model requires some features of the hardware tasks, including their computation time, size, the percent of critical bits, and the soft error rates of k-bit events (k ≥ 1) of the environment for the reliability estimation. Such an early estimation helps the developers to assess the reliability of their designs at earlier stages and leads to reduce the development cost. The proposed model has been evaluated by conducting several experiments on actual hardware tasks over different environmental soft error rates. The obtained results, endorsed by the 95% confidence interval, reveal the high accuracy of the proposed model. When comparing this approach with a reliability model (developed by the authors in a previous work) that does not consider the occurrence of multiple-cell upsets, an overestimation of the mean time to failure of 2.88X is observable in the latter. This points to the importance of taking into account multiple events, especially in modern technologies where the miniaturization is high.

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

This paper presents an optimized hardware architecture of the inverse quantization and the inverse transform (IQ/IT) for a high-efficiency video coding (HEVC) decoder. Our highly parallel and pipelined architecture was designed to support all HEVC Transform Unit (TU) sizes: 4 × 4, 8 × 8, 16 × 16, and 32 × 32. The IQ/IT was described in the VHSIC hardware description language and synthesized to Xilinx XC7Z020 field-programmable gate array (FPGA) and to TSMC 180 nm standard-cell library. The throughput of the hardware architecture reached in the worst case a processing rate of up to 1080 p at 33 fps at 146 MHz and 1080 p at 25 fps at 110 MHz when mapped to FPGA and standardcells, respectively. The validation of our architecture was conducted on the ZC702 platform using a Software/Hardware (SW/HW) enviro nment in order to evaluate different implementation methods (SW and SW/HW) in terms of power consumption and run-time. The experimental results demonstrate that the SW/HW accelerations were enhanced by more than 70% in terms of the run-time speed relative to the SW solution. Besides, the power consumption of the SW/HW designs was reduced by nearly 60% compared with the SW case.