A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

Federico Montaño,Jean Pierre David,Tarek Ould-Bachir

doi:10.3390/electronics9111838

Federico Montaño, Jean Pierre David + Show 1 more

Open Access

https://doi.org/10.3390/electronics9111838

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Journal: Electronics	Publication Date: Nov 3, 2020
Citations: 3	License type: CC BY 4.0

Affiliation: Polytechnique Montréal

Abstract

This paper presents a methodology for the design of field-programmable gate array (FPGA)-based real-time simulators (RTSs) for power electronic circuits (PECs). The programmability of the simulator results from the use of an efficient and scalable overlay architecture (OA). The proposed OA relies on a latency-insensitive design (LID) paradigm. LID consists of connecting small processing units that automatically synchronize and exchange data when appropriate. The use of such data-driven architecture aims to ease the design process while achieving a higher computational efficiency. The benefits of the proposed approach is evaluated by assessing the performance of the proposed solver in the simulation of a two-stage AC–AC power converter. The minimum achievable time-step and FPGA resource consumption for a wide range of power converter sizes is also evaluated. The proposed overlays are parametrizable in size, they are cost-effective, they provide sub-microsecond time-steps, and they offer a high computational performance with a reported peak performance of 300 GFLOPS.

Highlights

Hardware-in-the-loop (HIL) simulation is an industrial methodology used in the development of power systems to reduce risks and costs [1,2]
We propose a parametrizable and reconfigurable architecture inspired from overlay architecture (OA) that uses a modularized latency-insensitive design (LID) approach
Simulation results for an AC–DC–AC converter test case are presented and used to discuss the computational accuracy of the hardware solver (HS)

Summary

Introduction

Hardware-in-the-loop (HIL) simulation is an industrial methodology used in the development of power systems to reduce risks and costs [1,2]. Recent publications address the FPGA-based real-time simulation problem from an application, system or circuit modelling point of view [5,6,7]. Their purpose is either to reduce the simulation time-step, to propose new switch modelling techniques or to augment the parallelism of the simulation. The implementation of a HS follows a centralized design approach It consists of a datapath, comprised of memory elements and functional units (FU), under the command of a control unit that sequences all data transfers. We present an overview of OA and LID to clarify these concepts

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