An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

Ahmed Ben Atitallah,Rabie Ben Atitallah,Manel Kammoun

doi:10.3906/elk-1910-122

Ahmed Ben Atitallah, Rabie Ben Atitallah + Show 1 more

Open Access

https://doi.org/10.3906/elk-1910-122

Copy DOI

Abstract

This paper presents an optimized hardware architecture of the inverse quantization and the inverse transform (IQ/IT) for a high-efficiency video coding (HEVC) decoder. Our highly parallel and pipelined architecture was designed to support all HEVC Transform Unit (TU) sizes: 4 × 4, 8 × 8, 16 × 16, and 32 × 32. The IQ/IT was described in the VHSIC hardware description language and synthesized to Xilinx XC7Z020 field-programmable gate array (FPGA) and to TSMC 180 nm standard-cell library. The throughput of the hardware architecture reached in the worst case a processing rate of up to 1080 p at 33 fps at 146 MHz and 1080 p at 25 fps at 110 MHz when mapped to FPGA and standardcells, respectively. The validation of our architecture was conducted on the ZC702 platform using a Software/Hardware (SW/HW) enviro nment in order to evaluate different implementation methods (SW and SW/HW) in terms of power consumption and run-time. The experimental results demonstrate that the SW/HW accelerations were enhanced by more than 70% in terms of the run-time speed relative to the SW solution. Besides, the power consumption of the SW/HW designs was reduced by nearly 60% compared with the SW case.

Highlights

High-efficiency video coding decoder (HEVC) is one of the new video coding standards developed by the ITU and the ISO/IEC, specially designed to address all the crippling limitations of the H.264/AVC standard
The inverse quantization and the inverse transform (IQ/IT) hardware architecture is designed by dint of the VHSIC hardware description language (VHDL) language, simulated with the Mentor Graphics ModelSim simulation tool, and synthesized with two different technologies: the Loenardo Spectrum tool using TSMC 180nm standard cells and the Xilinx XC7Z020 field-programmable gate array (FPGA) with speed grade 3 using Xilinx vivado 2015.2
High performance hardware architecture of the IQ/IT is proposed in this paper that is used for the HEVC decoder

Summary

Introduction

Hardware architecture of IQ/IT Figure 9 describes the proposed architecture for the IQ/IT component of the HEVC decoder This architecture contains the inverse quantization and transform blocks as well as the control unit which is used to synchronize both the access and data processing of the whole design. The inverse quantization is applied and followed by 1D-IDCT/IDST for each column and row of TUs by exploiting the pipeline technique existing between both blocks This enables our architecture to receive 4 × 16 -bit quantized pixels simultaneously every 2 clock cycles and to process them simultaneously by means of the de-quantization block.

34 Clock cycles

Design

Conclusion