Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder

Abstract

The objective of the paper is to implement an area efficient hardware for intra prediction in high efficiency video coding (HEVC) decoder for DC, angular and planar modes of all block sizes. viz., \(64\times 64\), \(32\times 32\), \(16\times 16\), \(8\times 8\) and \(4\times 4\). The proposed hardware is written in Verilog and implemented in field programmable gate array (FPGA) Virtex-7. The clock cycles consumed by the proposed design is the lowest as compared to the existing designs [7] as in the proposed architecture all the three modes ( DC, angular and planar modes) are executed in parallel. The reference pixels are processed and one \(4\,\times \,4\) block is obtained at the output in one clock cycle as the architecture is designed to process 16 pixels (one 4 \(\times \) 4 block) in parallel for all the three modes. Once the prediction for one mode of a block is completed the resources are released and made available to be used by next mode or next block. Thus the resource consumption is less as compared to existing designs where all the modes for each block is executed irrespective of encoder information which results in unnecessary resource usage.