Abstract
The advent of space applications with increased computational requirements has led the space industry to consider innovative chips and avionics architectures for high-performance on-board data processing. In a relatively limited market, the European BRAVE family of Field-Programmable Gate Arrays (FPGAs) offers such novel radiation-hardened solutions. Towards verification, the current work devises and applies a methodology to thoroughly assess the BRAVE FPGAs and their SW tools. The paper focuses on NG-Large, i.e., the largest FPGA of the 65nm Radiation-Hardened-By-Design (RHBD) technology of NanoXplore to date. The proposed approach comprises a number of customized steps to systematically evaluate the entire FPGA design flow. Initially, we carefully select and tune a set of high-performance Digital Signal Processing (DSP) & Computer Vision (CV) benchmarks, which were originally developed as Hardware Description Language (HDL) IPs in past projects of the European Space Agency (ESA). Subsequently, we perform exhaustive exploration of the Synthesis, Placement, and Routing stages of the SW tools, as well as testing on actual HW boards. At each step, we generate and analyze a variety of results, while we also compare them to 3rd-party solutions. The results show that NG-Large provides sufficient programmability and performance, e.g., classic CV IPs for feature detection on megapixel images can achieve a throughput of 5–10 frames per second, while the on-chip memory utilization is up to 56% better than that of 3rd-party FPGAs. As a highlight, at system-level, we successfully implement and execute an entire HW/SW algorithmic pipeline for Vision-Based Navigation (VBN) involving SpaceWire data transfers with LEON CPU & NG-Large co-processing.
Highlights
The emerging need for increased computational power and fast data transfers in modern space applications makes the use of high-performance devices in on-board processing systems critical
Digital Signal Processing (DSP) AND COMPUTER VISION BENCHMARKS For the evaluation of NG-Large, according to our benchmark selection methodology, we created a set of 12 Hardware Description Language (HDL) benchmarks and selected 5 of them, which can be classified as follows: (i) FIR Filter for 1D signal processing, (ii) Harris Corner Detector and Canny Edge Detector for feature extraction, (iii) GAD-Disparity and Spacesweep for stereo matching [7]
The image is divided in horizontal stripes, which are downloaded to the Field-Programmable Gate Arrays (FPGAs) and processed successively by resource reusing
Summary
The emerging need for increased computational power and fast data transfers in modern space applications makes the use of high-performance devices in on-board processing systems critical. Radiation-hardened CPUs, such as the PowerPC-based RAD750 (12W@200MHz) and LEON2based AT697F (1W@100MHz), seem unable to meet the. V. Leon et al.: Development and Testing on the European Space-Grade BRAVE FPGAs bilities [1]. Leon et al.: Development and Testing on the European Space-Grade BRAVE FPGAs bilities [1] In this context, the new NanoXplore [2] RHBD family of FPGAs [3], [4], known as BRAVE, is expected to play a key role in upcoming space missions, especially in Europe. The BRAVE family offers high resource density on FPGA and SW tools for end-to-end development, as well as seamless re-configuration
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