High-Resolution Time-to-Digital Converters Implemented on 40-, 28-, and 20-nm FPGAs

Abstract

This work proposed the implementations of high-resolution time-to-digital converters (TDCs) on field-programmable gate array (FPGA) platforms with different manufacturing technologies: 40-nm Virtex-6, 28-nm Kintex-7, and 20-nm Kintex UltraScale. The large-scale multiphase matrix (LSPM) structure is employed, which is different from the commonly used delay line structure. Experimental results have proved that all the three implementations have achieved competitive resolution. In particular, the Kintex-7 LSPM-TDC has achieved a resolution of 1.29 ps, ranking among the best performing FPGA-based TDCs. The dynamic ranges of the Virtex-6, Kintex-7, and Kintex UltraScale TDCs are 22, 11, and 18 s, respectively. The LSPM-TDCs implemented on Virtex-6, Kintex-7, and Kintex UltraScale have demonstrated equivalent dynamic range as the state-of-the-art FPGA-based TDCs, but without using the “two-stage” method that worsens the precision. Moreover, experiment and comparison between implementations with different manufacturing technologies are provided. With the technology advances from 65 to 28 nm, steady improvements in resolution are acquired. However, the 20-nm Kintex UltraScale performs not as good as the 28-nm Kintex-7. Experimental results also demonstrate that the phase noise and dynamic power consumption are reduced in platforms with more advanced technology. The discussion of routing delay and jitter of the reference clock provides a reference for FPGA designs.