Digital Circuit Design Research Articles

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques

Critical path replica (CPR) is a widely used technique in synchronous digital circuit design. However, the existing CPR technique cannot accurately reflect the timing of the circuit due to local process variations (LPV). An improved CPR technique based on load capacitance matching (LCM) is proposed in this paper, which can track critical path delay across wide voltage range. The impact of LPV is simulated under wide voltage range, and a configurable delay line is designed to eliminate the effect of LPV. Furthermore, a low overhead mixed-threshold transition detector (TD) circuit is also proposed to monitor timing violations of the replica path, which generate an ‘error’ signal used to dynamically regulate the chip’s operating voltage. The proposed techniques are implemented on a CORDIC chip using the 55-nm CMOS process. Simulation results show that in the near-threshold voltage (NTV) region, the supply voltage can be reduced from 0.8 to 0.6 V, enabling a maximum of 42.6% power saving at the TT corner, 25°C with lesser than 1% area overhead as compared to the baseline design.

An Ultra-Energy-Efficient Reversible Quantum-Dot Cellular Automata 8:1 Multiplexer Circuit

Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature.

CNTFET-based digital arithmetic circuit designs in ternary logic with improved performance

Ternary logics are more desirable than the binary logic because it offers high speed operations and large density of information in digital logic systems. The carbon nanotube field-effect transistors (CNTFETs) are considered as better option for designing the ternary circuits because it provides the multiple threshold voltages by changing nanotube diameter. The complex arithmetic schematics such as adders and multipliers are important circuits in many VLSI applications. The ternary half-adder (THA) and multiplier (TMUL) designed using the Stanford 32 nm CNTFET are proposed in this study. The proposed THA and TMUL uses 41 and 33 CNTFETs and that resulting in a 54.44 % and 45 % reduction in transistor count, which plays major role for delay and power optimization. As a result, the proposed THA shows 37.01 %, 14.07 %, and 45.87 % improvement in delay, power, and energy, whereas TMUL shows 30.48 %, 6.64 %, and 36.74 % improvement in delay, power and energy, respectively, compared to existing circuits. The proposed THA and TMUL are developed using HSPICE with 0.9 V as a supply voltage.

Research on the design and model of ideological and political teaching of the “Digital Circuit and Logic Design” course

Since the Ministry of Education put forward the requirements of promoting the ideological and political construction of college courses, colleges, and universities have actively designed and explored various professional courses’ ideological and political teaching construction. Taking “Digital Circuit and Logic Design” as an example, this paper constructs the teaching design, teaching model reforms, and the evaluation method of the practical approach by analysing the course’s characteristics, objectives, and current situation. It discusses the implementation path of promoting the ideological and political education of the “Digital Circuit and Logic Design” course.

Memristor-Inspired Digital Logic Circuits and Comparison With 90-/180-nm CMOS Technologies

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1 mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density Y <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> O <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3}}$</tex-math> </inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Notice of Violation of IEEE Publication Principles: Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate

Notice of Violation of IEEE Publication Principles “Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate” by Suhaib Ahmed and Syed Farah Naz in IEEE Transactions on Circuits and Systems II: Express Briefs After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE’s Publication Principles. This paper contains significant portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. “Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata” By Haotian Chen, Hongjun Lv, Zhang Zhang, Xin Cheng and Guangjun Xie in Journal of Circuits, Systems, and Computers, Vol. 28, No. 8, 2017 The advantages such as high operating frequency (in the range of few THz), low power dissipation, small size and high density in the nano regime has led to the application of Quantum dot Cellular Automata (QCA) in designing various digital circuits. In this brief, an ultra-efficient two input XOR gate design in QCA is proposed. It is a single layer design consisting of only 9 cells with no crossover and operating on cell to cell interaction. The functionality of the proposed gate has been verified at both physical and simulation level. In addition to this, fault tolerance to single cell missing defect, single cell addition defect and single cell displacement defect of the proposed XOR gate has also been presented. Based on the performance evaluation, it is seen that the proposed XOR gate has least cell count, least area and least latency which in turn leads to least circuit cost. Also, the proposed design dissipates least energy. The applicability of proposed XOR gate has also been investigated by designing various cost efficient digital circuits such as full adder, parity checker, etc.

Difference Adder Graph Algorithm for Reducing LUT Size

The current study introduces an implementation of the Difference Adder Graph Algorithm (DAGA) using Verilog. DAGA, rooted in graph theory and adder circuits, aims to diminish Look Up Tables (LUTs) and power consumption in Field Programmable Gate Arrays (FPGAs). By reducing the number of LUTs required for a specific functionality, DAGA offers a promising alternative for digital circuit optimization. To evaluate its efficacy, the paper contrasts DAGA with the Multiple Constant Multiplication (MCM) method, which leverages Carry Save Adder (CSA) architecture and exploits signed-digit number representations to minimize LUT usage. Experimental findings reveal DAGA's superiority over MCM in both area and power utilization reduction. Implementation details and results indicate a remarkable 49.29% reduction in LUT count and a corresponding 41.8% decrease in power consumption for digital circuits. These outcomes underscore the effectiveness of DAGA in enhancing FPGA efficiency, highlighting its potential as a valuable tool for digital circuit designers seeking to optimize performance and power utilization.

Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques

Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques

IT vertical: concept and implementation of studying information technologies in basic school

The article presents a description of the concept and model for the study of information technologies at the level of basic general education in the context of the implementation of the Federal State Educational Standards. Based on the example of the implementation of the project in grades VII—IX of general education organizations in Moscow, the content of the educational trajectory of a teenager is revealed, taking into account the request for early profiling in the field of "Informatics and information technologies". Features of the educational trajectory are implemented through a special bilingual programming course, new content of the course of technology (with the inclusion of special sections on mechatronics, technologies for creating digital twins, electronics and circuit design) and an ecosystem of extracurricular activities courses in forms specific to software developers. A feature of studying informatics and physics at an advanced level is the presence of interdisciplinary cases using digital laboratories. Mechanisms and tools for integrating specialized knowledge on current issues in the IT industry into the educational program are presented. A special place is occupied by the issues of creating the necessary infrastructure for the implementation of the project: material and technical base, personnel training and methodological support of the project. The unique functional and didactic capabilities of digital tools for active immersion of schoolchildren in the process of mastering the content of the educational program are presented. Examples of author's assignments are given for developing the skills of schoolchildren, diagnosing and monitoring acquired knowledge.

Design of an interface circuit system for mode-separation MEMS digital gyroscope

In this paper, a novel digital closed-loop interface circuit system of MEMS vibrating gyroscope is proposed, which includes driving, detection and quadrature circuits. Because of the high sensitivity and precision of the MEMS gyroscope, the interface circuit system is established under the condition of mode separation. The driving circuit of MEMS gyroscope adopts digital automatic gain control (AGC) to realize self-excitation closed-loop control, which makes the gyroscope system simple in structure and good in robustness. First, the working principle of the gyroscope’s sensitive structure is introduced and the system simulation model of the sensitive structure is developed. Second, a [Formula: see text] ADC and DAC with single-bit output are designed and the feasibility of the driving circuit design is verified by the system-level model. Third, the quadrature closed-loop correction circuit is designed to reduce the coupling of the quadrature component to the gyroscope detection circuit. The simulation results show that the quadrature correction loop can effectively reduce the influence of the quadrature coupling on the detection loop of MEMS gyroscope. Finally, the system-level model of the gyroscope is established by SIMULINK, the overall system performance of the gyroscope is analyzed, and the test system of MEMS gyroscope is built by field-programmable gate array (FPGA) and application specific integrated circuit (ASIC). The experiment verifies the feasibility of the digital interface circuit design, and the zero-bias instability of the gyroscope system is 1.0∘/h.

Transistor Self-Heating-Aware Synthesis for Reliable Digital Circuit Designs

Transistor Self-Heating-Aware Synthesis for Reliable Digital Circuit Designs

Review on Reversible Logic Gates

Abstract: Reversible logic gates have emerged as a pivotal area of research in the field of digital circuit design, offering the promise of ultra-low power consumption. This survey paper comprehensively explores the foundations and practical applications of reversible logic gates. Beginning with an introduction to the fundamental principles of reversibility, it delves into the design of reversible gates, covering CNOT, Feynman, Toffoli, Peres, Fredkin gates, and beyond. The paper offers a systematic review of state-of-the-art research in the field, discussing various optimization techniques and quantum-inspired reversible circuits. It also investigates real-world applications, ranging from low-power VLSI design to quantum computing. By summarizing the key findings, challenges, and potential future directions in reversible logic gate design, this survey paper provides a valuable resource for researchers, engineers, and enthusiasts seeking a comprehensive understanding of this transformative technology

Recurrent neural network implementation of digital integrated circuits to mitigate challenges in design verification

Design verification is the dominant stage that consumes the most resources in the digital integrated circuit (IC) design process. Design verification is important because human designers imperfectly convert high-level specifications to low-level circuit implementations using standard cell logic, which is nonlinear and complex to predict and characterize. The widening process variations in shrinking process technologies while digital designs grow in scale and complexity to the extent of being impossible to fully or intuitively identify all temporal interactions of a specific design. Deep neural networks (DNN) are being progressively integrated into the sophisticated software tool chain and design process flow of digital IC as artificial intelligence can learn relationships and correlations in complex, high-dimensional, and multi-factorial problems. In this work, we propose to apply DNN to implement digital IC to minimize the complexity of digital design verification. We posit that DNN can learn to implement circuit functions directly from high-level specifications without requiring detailed specifications from the designer. Trained neural networks can be implemented on neuromorphic hardware to achieve greater power and compute efficiencies than the conventional standard cell implementation. We demonstrate that over 150 randomly generated finite state machines (FSM) can be learned effectively with Recurrent Neural Network (RNN) comprising Gated Recurrent Units (GRU) with different complexity as indicated by the number of states and inputs to the FSM. Our proposed methodology of learning RNN GRU implementations of FSM demonstrates a way forward to reduce the cost and effort of design verification, ultimately leading towards faster digital IC design cycles.

GA evolved CGP configuration data for digital circuit design on embryonic architecture

Embryonic architecture that carries self-evolving design with fault tolerant feature is proposed for deep space missions. Fault tolerance is achieved in the embryonic architecture due to its homogeneous structure. The cloning of configuration data or genome data to all the embryonic cells makes each cell capable of selecting required cell function using selective gene. The primary digital circuits of avionics are implemented on the fabric, where the configuration data in Cartesian Genetic Programming (CGP) format is evolved through customized GA. The CGP format is preferred over LUT format for the circuit configuration data due to its fixed data size in case of modular design. Further the CGP format enables fault detection at embryonic cell level as well as logic gate level. The various combinational and sequential circuits like adder, comparator, multiplier, register and counter are designed and implemented on embryonic fabric using Verilog. The circuit performance is evaluated using simulation. The proposed PHsClone genetic algorithm (GA) design with parallel-pipeline approach is to achieve faster convergence. Four concurrent PHsClone GA executions (four parallel threads) achieve convergence for the 10 times faster for a 1-bit adder, and 3 times faster for a 2-bit comparator.

Design and Implementation of Hybrid Multiplier for DSP Applications

In recent decades, there has been a consistent reduction in feature sizes in integrated circuit (IC) technology, leading to the need for increased placement of functional circuits on each chip. When it comes to the design of digital circuits, there is a significant focus on hybrid logic. Hybrid logic is highly regarded due to its ability to consume less power while achieving higher efficiency. Hybrid logic circuits have similarities to complementary metal-oxide-semiconductor (CMOS) transistors, yet possess a reduced transistor count while offering enhanced performance and reliability capabilities. This study examines the modeling and implementation hybrid multiplier with of help of hybrid adder. The functionality of adder is determined with the help of hybrid logic producing XOR/XNOR functionalities in single circuit. The proposed hybrid Multiplier, which incorporates a hybrid Adder, has been successfully designed and implemented using CMOS 45nm technology and Mentor Graphics software the hybrid transistor logic multiplier demonstrates a decrease in total delay of 60% compared to CMOS.

Design of electronic clock and stopwatch based on FPGA and VHDL language

This paper designs a simple system that can include electronic clock and stopwatch based on FPGA(Field Programmable Gate Array) and VHDL(Very-High-Speed Integrated Circuit Hardware Description Language). The first chapter briefly introduces the research background. The second chapter introduces the theoretical basis of digital circuits and the hardware and software platform used in this paper. In the third chapter, the design of each sub-module of the system and the overall design of the system are carried out. This chapter is the core chapter of this article, which describes the functions of the module and explains the input and output ports. In this chapter, a core point of digital circuit design is reflected: combining modules that realize simple functions into modules that can realize complex functions. And integrate sub-modules that realize similar functions into a top-level module. The fourth chapter is the logic synthesis of the circuit. The fourth chapter shows the simulation of the core module function and the simulation of the system output. The conclusion section summarizes the interesting parts of the design of this paper.

Fusion of powerful features of Harris Hawks with Cuckoo Search algorithm for engineering applications

The High-level synthesis (HLS) is a key step in the digital VLSI circuit design. HLS can be seen in the present study as an important matter of intelligently map a Data Flow Graph (DFG) specification of digital filters to FPGA. In this article, the powerful features of the Harris hawks optimization (HHO) and Cuckoo search (CS) algorithm have improved the performance of the proposed method. This proposed strategy is also known as the GChO algorithm. In GChO, the phase of CS helps to force the HHO to escape from stagnation, to ignore local optima and premature convergence. In addition for HLS, the three retiming-based models were also proposed in the work. The standard pipelining was employed in Model 1. The modified Min-Period Retiming on the multiplier less digital filters was incorporated by Model 2 and led to a significant improvement in clock frequency. Model 3 adopted modified Min-Area Retiming on digital filters and reduced the complexity of the circuit; however these designs therefore offer single parameter-based heuristic solution. This can be resolved by using meta-heuristic approach focused on retiming. The use of meta-heuristic methods and swarm intelligence has been considered as a highly desirable choice when searching the digital block solution space with higher frequency and reduced complexity in HLS problems. The robustness of the GChO method has been verified on IEEE CEC’ 2020 standard benchmark test suites. The paper analyzes that the performance of the proposed GChO algorithm outperforms the Harris hawks optimization (HHO), Moth Flame optimization algorithm, Particle Swarm optimization algorithm, Chimp optimization algorithm for the HLS digital filters. The experimental results show that the proposed Model 2 and 3 for retimed PDR-FIR filter is improved in term of MUF by 7.38% and utilized slices by 37.77%, PRO-DFII IIR retimed filter by 10.54%, and complexity reduced by 29.69%, PRO-LAT-ARF by 41.61% and slice by 11.17% and PRO-LATLAD-IIR improved in term of MUF, slices by 35.69% and 38.095% in relative to the standard retimed filters of various architecture. For the evolutionary GChO-retimed filter, an improvement in MUF by 58.52%, and utilized slices by 49.61%, for PDR-FIR, 48.09%, 80.76% for PRO-DFII-IIR , 52.68%, 54.33% for PRO-LAT-ARF, 27.85% and 18.46% for PRO-LATLAD-IIR are achieved in respect of Model 2 and 3 whereas an improvement in term of MUF by 34.60%, and utilized slices by 37.61%, for PDR-FIR, 40.55%, 39.66% for PRO-DFII-IIR, 40.08%, 31.33% for PRO-LAT-ARF, 26.95%, 24.41% for PRO-LATLAD-IIR are achieved with respect of other meta-heuristic methods.

Deep transfer learning approach for digital circuits vulnerability analysis

Hardware Trojans (HT) are the most malicious components attacking modern integrated circuits (ICs). Information leakage, incorrect functionality, and overheating are the major effects of HT insertion. Due to the outsourcing of multi-stage digital circuit design and fabrication, HTs can be inserted by rogues at every stage. The types of HTs and insertion methods evolve continuously and their detection becomes more complex. Consequently, designing integrated circuits robust to HT insertion seems efficient. A prerequisite for such a strategy is the evaluation of integrated circuit vulnerability to HT insertion. There are several factors involved in the vulnerability of fabricated integrated circuits such as the distribution of white spaces in the IC layout, the ratio of unutilized routing resources, the amount of activity of the circuit’s nodes, the geometrical properties of the circuit’s gates, the delay of various paths, and etc. The interrelation of these diverse factors makes IC vulnerability modeling a challenging problem. In this paper, a deep neural network (DNN) based approach is developed to combine all the effective factors in IC vulnerability analysis. Firstly, we generate a comprehensive dataset containing various types and sizes of hardware Trojans inserted into benchmark circuits. The benchmark circuits used in this study are ISCAS 85, ISCAS 89, and ITC 99. Then using the transfer learning concept seven state-of-the-art deep convolutional neural networks are trained and verified using the constructed dataset to classify every integrated circuit into three vulnerability levels (low, moderate, and highly vulnerable classes). Simulation results show that our proposed method achieves almost 95 % accuracy in the most successful case (VGG16). The lowest accuracy belongs to Inception V3 (∼87.65 %) which is much better than the most successful previous studies (72 %). This is mainly because the DNN-based method handles shortcomings (such as incomplete modeling of vulnerability-related factors) in the previous state-of-the-art methods efficiently.

A near‐DC measurement and modelling of low‐frequency noise in electronic components

AbstractLow‐frequency noise, generated inherently by the number or mobility fluctuation of carriers, is a crucial concern for the design of analog and digital circuits. Unified modelling based on experimental validation of near‐DC noise in amplifiers is a long‐standing open problem. This article develops a model for low‐frequency noise by deriving new bounds for carrier capturing and releasing. According to the proposed model, a measurement system is suggested that operates in a wide frequency range and even at very low frequencies. The system is noise‐tolerant, since the amplifier is selected based on acceptable noise levels. Among the advantages are the independence from specialized structural noise models for each component and the low cost of the measurement system. The evaluation results show that the proposed method leads to a promising improvement in the low‐frequency noise measuring and is superior to conventional models in the normalized root mean square error indicator. Findings reveal that the proposed measurement method can estimate the flicker noise around the DC frequency, and the proposed model agrees reasonably with the proposed measurement circuit.

Implementation And Comparison of Different Stages of Current Starved CMOS Ring Oscillator – A Study

The ring oscillators serves as the fundamental building blocks in both digital and analog circuit design, as its extensive use is found in various electrical systems, including phase-locked loops, frequency dividers, and clock generators. This study gives a general overview of the ring oscillator circuit, including its workings, uses, and important design considerations. The ring oscillator generates timing signals for synchronous operation and is often employed as a clock generator in digital systems. It may also be used as a frequency divider to separate higher frequencies into lower ones. A closed loop is used to connect an odd number of inverting stages to create the ring oscillator circuit. An inverter, which is often built using complementary metal-oxide-semiconductor (CMOS) technology, is a component of every stage. By adding a delay to each step, the ring oscillator creates a self-sustaining oscillation. The development and comparison of 3, 5, and 7 stage ring oscillators for different performance metrics, as well as corner analysis for propagation delay and the effect of temperature on the operation of the ring oscillator was performed using Cadence Virtuoso with 90nm technology. This comparison of several phases of a current-starved (CS) ring oscillator offers an advantage to the best design with innovation based on the technology employed and outcomes from the corner analysis, which hasn't been done in any of the more recent researches.