Digital Circuit Design Research Articles

Asynchronous Circuit Principles and a Survey of Associated Design Tools

Planning and implementing a semiconductor integrated circuit is a highly complex process. Although physical limits seem to be approaching, it currently follows a growing evolutionary path. As deep submicron technologies evolve towards perhaps even sub-nano geometries, the design process complicates accordingly. Once subtle in higher geometry nodes, some effects become relevant or even dominant. Examples are effects that tamper the reliability of wires, such as crosstalk, or the adequate behaviour of gates, such as the increasing sensitivity to single event effects. Design techniques must thus also evolve, to provide a wide range of tools to deal with new effects during the integrated circuit design and test processes. This tutorial covers one set of design techniques that is often overlooked, but which can reveal themselves instrumental in dealing with the mentioned technology evolution, the use of clockless or asynchronous circuits. The tutorial is divided into three parts: first it introduces a metamodel for the digital circuit design process enabling to reason about distinct design styles; second, it covers the main principles of asynchronous circuit design, differentiating it from mainstream circuit design techniques such as conventional synchronous design; the third and last part presents a set of tools and systems that can be employed to effectively design asynchronous design, with emphasis on material that can be used to produce manufacturable circuits and systems, often associated to commercial integrated circuit synthesis, implementation and test tools and frameworks.

VirtualSync+: Timing Optimization With Virtual Synchronization

In digital circuit designs, sequential components such as flip-flops are used to synchronize signal propagations. Logic computations are aligned at and thus isolated by flip-flop stages. Although this fully synchronous style can reduce design efforts significantly, it may affect circuit performance negatively, because sequential components can only introduce delays into signal propagations but never accelerate them. In this article, we propose a new timing model, VirtualSync+, in which signals, specially those along critical paths, are allowed to propagate through several sequential stages without flip-flops. Timing constraints are still satisfied at the boundary of the optimized circuit to maintain a consistent interface with existing designs. By removing clock-to-q delays and setup time requirements of flip-flops on critical paths, the performance of a circuit can be pushed even beyond the limit of traditional sequential designs. In addition, we further enhance the optimization with VirtualSync+ by fine-tuning with commercial design tools, e.g., design compiler from Synopsys, to achieve more accurate result. To achieve this fine-tuning, we first optimize the circuits by reallocating sequential components with sequential and combinational components as delay units. Afterward, the removal locations of flip-flops with respect to the circuits under optimization are extracted and the corresponding wave-pipelining timing constraints compatible with commercial design tools are established. These timing constraints are then incorporated into the optimization flow of commercial tools to generate the optimized circuits. The experimental results demonstrate that circuit performance can be improved by up to 4% (average 1.5%) compared with that after extreme retiming and sizing, while the increase of area is still negligible. This timing performance is enhanced beyond the limit of traditional sequential designs. It also demonstrates that compared with those after retiming and sizing, the circuits with VirtualSync+ can achieve better timing performance under the same area cost or smaller area cost under the same clock period, respectively.

An Online Course Content for Undergraduate Students on Full-Custom Design of a Digital VLSI Circuit Using Open-Source Software

The Very Large-Scale Integration (VLSI) circuit design is a promising field for undergraduate students hoping to explore job opportunities in electronics circuit design companies. Therefore, several institutes in India offer VLSI courses to electronics engineering undergraduate students. In recent times, because of the pandemic, online classes appeared as an effective method of teaching; this helped in running of academic schedule smoothly without hampering the students’ learning process. In this paper online teaching content is presented to help the student learn digital VLSI circuit design using an open-source tool. This course content is particularly helpful in understanding the theoretical and practical design of a Complementary Metal Oxide Semiconductor (CMOS)-based logic function, with minimal effort by the faculty without access to campus software. The content starts with a digital logic function and its switch-level representation into PULL-UP and PULL-DOWN networks. Then the switch-level circuit with the help of Euler’s graph is translated into a stick diagram and then converted into a layout cell using the lambda design rule. An interesting approach to choosing the gate sequence in the stick diagram from Euler’s graph, and the simulation result of the layout cell are presented and discussed. The approach helped the students in understanding full custom CMOS logic function design, test, and validation, with less effort and time. The survey shows that 86% of the students were satisfied with the content and that the course content helped to achieve an 81% average pass percentage in the two online semesters.

Novel high-performance QCA Fredkin gate and designing scalable QCA binary to gray and vice versa

In the design of digital logic circuits, QCA technology is an excellent alternative to CMOS technology. Its advantages over CMOS include low power consumption, fast circuit switching, and nanoscale design. Circuits that convert data between different formats are code converters. Code converters have an essential role in high-performance computing and signal processing. In this paper, first, we proposed a novel QCA structure for the quantum reversible Fredkin gate. Second, we proposed 4-bit and 8-bit QCA binary-to-gray converter and vice versa. For the second proposal, both reversible and irreversible structures are suggested. The proposed structures are scalable up to N bits. To change the conversion type from B2G to G2B, we use a 2:1 QCA multiplexer. The proposed QCA Fredkin is applied in the reversible design of QCA code converters as multiplexers. The suggested designs are simulated using the QCADesigner tool. Then we calculated figures of merit, including cell counts, occupied areas, and clock zones. Finally, we compare the proposed structures to existing research. Our proposed approach is the first quantum-dot cellular automata design to perform B2G conversion and G2B in a single QCA circuit. The proposed designs are scalable. Specifications are reported.

An Artificial Neural Network Model for Electro-Thermal Effect Affected Hot Carrier Injection Reliability in 14-nm FinFETs

FinFETs have a bright future for advanced analog/RF and digital circuit design in 5G/6G technology. As the integration density increases, the self-heating effect (SHE) becomes more severe, and the hot carrier injection (HCI) reliability of FinFETs further deteriorates since it is highly dependent on temperature. In this article, an artificial neural network (ANN) model for HCI prediction is proposed for 14-nm FinFET with consideration of SHE under various voltage stresses and environment temperature. The HCI numerical simulation can be mainly divided into two parts: 1) the temperature responses for the device under different stresses are obtained by numerically solving time-dependent thermal conduction equation with heat generation in the nanoscale FinFET and 2) based on the transient temperature response to different stress voltages, HCI-induced threshold voltage shift (TVS) as a function of time is captured numerically. Our HCI-induced TVS simulation results agree well with others’ experiment results, which verifies the simulation methods. An ANN model is then developed to predict the TVS induced by HCI with the training data obtained from numerical simulations. The ANN model has good accuracy with an average relative error of 0.36% in predicting TVS and greatly reduces simulation cost once the ANN model is built for the HCI prediction of FinFETs, which has great potential for reliability design in circuits and systems.

Design of Ternary Logic Circuits using Pseudo N-type CNTFETs

In this paper, a novel method is presented to design ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed and reduced chip area. The digital logic circuit designs are developed using Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The threshold voltage of CNTFETs is altered by the CNT diameter that is defined by the chirality vector. The ternary inverters such as standard inverter (SI), positive inverter (PI) and negative inverter (NI) and ternary basic gates such as AND, NAND, OR and NOR gates are designed. Furthermore, the half adder circuits developed which assists to develop complex circuit schematics. The proposed ternary schematics are designed and simulated using the HSPICE simulator. Moreover, the performance of the proposed circuits are investigated in terms of delay, power dissipation and power delay product (PDP) and compared with the existing circuits. It is observed that the proposed circuits show average performance improvement up to 47.48% over the existing circuits.

Noise Effects in the Design of Digital Circuits Based on CNTFET

In this paper initially we present two CNTFET models: the first, already proposed by us and the second the Stanford model, recalling our method to match the output characteristics and transconductance characteristics between these two models. Then we briefly recall a compact noise model, proposed by us, used to simulate the performance of some digital CNTFET circuits, for which we present the DC, transient and noise analysis. In particular we examine a inverter gate and the proposed analysis allows to determine the optimal value of input voltage which makes the noise effects negligible.

Design of Gene Boolean Gates and Circuits with Convergent Promoters.

Gene digital circuits are the subject of many research works due to their various potential applications, from hazard detection to medical diagnostic. Moreover, a remarkable number of techniques, developed in electronics, can be used for the construction of biological digital systems. In our previous works, we showed how to automatize the design and modeling of gene digital circuits whose gates were based on transcription and translation regulation. In this chapter, we illustrate how Boolean gates could be implemented by following a particular architecture, the convergent promoter one, rather diffuse in nature but seldom adopted in Synthetic Biology. Beside gate design, we also explain how to extend our previous modeling approach, based on composable parts and pools of molecules, to quantitatively describe and simulate this particular kind of digital biological devices.

Special Issue on Design of Fault-Tolerant Digital Circuits and Systems

As technology scales down, the speed and power efficiency of digital circuits become greatly enhanced [...]

Design of Efficient AI Accelerator Building Blocks in Quantum-Dot Cellular Automata (QCA)

Digital circuit design technologies based on Quantum-Dot Cellular Automata (QCA) have many advantages over CMOS, such as higher intrinsic switching speed up to Terahertz, lower power consumption, smaller circuit footprint, and higher throughput due to compatibility of the inherent signal propagation scheme with pipelining. Hence, QCA is a perfect candidate to provide a circuit design framework for applications such as Artificial Intelligence (AI) accelerators, where real-time energy-efficient performance needs to be delivered at low cost. A novel QCA design approach based on optimal mix of Majority and NAND-NOR-INVERTER (NNI) gates with USE (Universal, Scalable, Efficient) clocking scheme, has been investigated in this work for latency and energy consumption improvements to fundamental building blocks in AI-accelerators, including multipliers, adders, accumulators and SRAMs. The common <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times 4$ </tex-math></inline-formula> Vedic multiplier has been redesigned using the proposed approach, and simulated to yield 62.8% reduction in cell count, 82.2% reduction in area, and 71.2% reduction in latency. 83% reduction in cell count, 94.5% reduction in area, and 94.6% reduction in latency was simulated for the proposed 8-bit PIPO register. The proposed SRAM cell design is estimated to have similar improvement figures to those achieved by the sub-blocks, such as the D-Latch, which has been simulated to exhibit 44.4% reduction in cell count, 50% reduction in both area and latency, and 73% reduction in energy dissipation. The contributions from this work can be directly applied to low cost, high throughput, energy efficient AI-accelerators that can potentially deliver orders of magnitude better energy-delay characteristics than their CMOS counterparts, and significantly better energy-delay characteristics than state-of-the-art QCA implementations.

Transfer of Analogies in Traditional Programming Languages to Teaching VHDL

One of the languages available to describe a digital system in FPGA is the VHDL language. Since programming in hardware requires a different way of thinking than developing software, the students face some difficulties when trying to design in VHDL language with the previous and long experiences kept in mind in the learning of software imperative programming. These are its concurrency, parallel and sequential model. Due to the insufficient understanding of these topics, it is difficult for students to master the VHDL language. Analogies change the conceptual system of existing knowledge by linking the known to the unknown and by changing and strengthening their relationships. This study contributes to overcoming the problems that students encounter in the coding of the above-mentioned topics in VHDL language by using their experiences in traditional programming languages through analogies. Analogies were used in an undergraduate embedded systems course to explain complex concepts such as those related to signals, concurrent/parallel process; and to encourage comprehensive projects in digital circuit design. In feedback from students, the discussion and negotiation of analogies seems to minimize confusion and from using inappropriate expressions in using VHDL language.

A Delta Sigma Modulator-Based Stochastic Divider

The divider is one of the most complex hardware units in Stochastic Computing (SC); even though several new designs have been presented to reduce the computation latency of the conventional divider, all of them still require a considerable number of clock cycles. Moreover, they incur in low performance due to the employed arithmetic computational scheme. In this paper, a Delta Sigma Modulator (DSM) based stochastic divider is proposed. As an entirely digital circuit, the proposed divider offers the best computation latency and accuracy over all existing stochastic dividers found in the technical literature (with a typical reduction between 66.8% and 96.9% in the number of clock cycles and a reduction from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{\mathrm {-3.4}}$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{\mathrm {-3.9}}$ </tex-math></inline-formula> in the average mean square error for a 10-bit resolution). An SC-based Neural Network (NN) is considered as an initial case study to evaluate the advantages of the proposed design in an emerging application; results show that the proposed divider enables an SC-based NN to achieve a higher classification accuracy and hardware efficiency than existing designs. To show the flexibility of the proposed divider design, its application to Sobol-based sequences is also presented; also in this case, its superiority over other designs is confirmed. These features make the proposed design very attractive for hardware-constrained platforms; moreover, such a novel design approach that incorporates ideas from analog/mixed signal circuit design into a digital circuit design, can motivate other researchers to design efficient SC designs using similar schemes.

Boolean Subtraction and Division with Application in Blood Transfusion

The subject of Boolean subtraction and division first appeared in the gem Laws of Thought by George Boole of Great Britain. However, this subject has been exiled from the famed Boolean algebra because it was supposed that it leads to illogical expressions. A paper recently published elsewhere by the author reintroduced the subject by clarifying it and then furnishing an application of it in the design of digital circuits. The goal of this work is to demonstrate how these banished logical operations can be employed in furnishing infallible information about blood typing and cross-matching during blood transfusion.

Study of analog-to-digital mixed integrated circuit configuration using number theory

Electronic circuits form the basis of much of the technology we use today. Professor Haruo Kobayashi and Assistant Professor Anna Kuwana, Division of Electronics and Informatics, Gunma University, Japan, are utilising classical mathematics, including theorems such as number theory and control theory in their design of circuits that contain elements of analogue signalling. Analogue circuit planning is regarded as an art as these circuits are typically designed based on mature designers' intuition and experiences in a process that is less systematic for coming up with new architectures and more designing than digital circuit design and Kobayashi and Kuwana firmly believe that 'beautiful' mathematics can facilitate truly great circuit design. Additional mathematics techniques employed by Kobayashi and the team are statistics, coding theory, modulation and signal processing algorithms and pairing pure mathematics theorems with electrical engineering is a key feature of the researchers' work. The team utilises theoretical analysis and simulations such as the circuit simulator (SPICE) and system simulator (MATLAB) to test its work and collaborates with semiconductor companies and electronic measurement instrument companies in Japan for smart circuit design and effective circuit testing. So far, results include that using SAR ADC configurations with Fibonacci sequence weights can improve the speeds and reliability of the SAR ADC. Also several new DAC architecutures and waveform sampling methods are derived based on mathematics.

Performance investigation of Ge DLTFET based digital integrated circuit

ABSTRACT The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications.

Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods

This Project details about the design of D Flip Flop (DFPFP). This D Flip Flop circuit is analyzed by using the supply voltage level methods. These methods are used mainly to suppress the power consumption caused due to leakage currents. In addition, because of this implemented technique, the time taken for battery backup, and the supply voltage given at standby mode gets minimized. The projected circuit uses a smaller number of transistors, such that power consumption and leakage currents are in prior limit. Mainly, the CMOS D Flip Flops are designed to use them in binary counters, shift registers, Analog and Digital circuit designs. And this circuit design is implemented in 45nm CMOS Technology Cadence Virtuoso Tool.

High performance 2n:1:2n reversible MUX/DMUX architecture for quantum dot cellular automata

AbstractQuantum‐dot Cellular Automata (QCA) lead to fundamental changes in nanoscale technology. It promises small area, low power, &amp; high‐speed structures for digital circuit design. This paper presents efficient low power structures of reversible multiplexer &amp; demultiplexer (RMD) modules based on the QCA technology. The simulation result shows that the proposed RMD module has utilized less area &amp; low power consumption. The simulation, layout, &amp; energy dissipation of the proposed RMD module have been carried out using the QCA Designer‐E simulation tool.

Optimal Recognition of Volleyball Player’s Arm Movement Track Based on Embedded Microprocessor

An embedded microprocessor is the core part of the integrated circuit system, and it represents one of the highest levels of a digital integrated circuit design. Therefore, the design of low-power embedded microprocessors has become an important research direction in the integrated circuit design. Volleyball has always been a very important sport in our country, and it is a sport that the masses of people like to see. The basic techniques of volleyball include ready posture and movement, serving, hot ball, passing, smashing, and netting. The research content of this article is a simulation study of volleyball players’ arm trajectory optimization recognition. In response to the above problems, this paper proposes an optimized recognition method based on the volleyball player’s arm motion trajectory. The simulation results show that the method has high recognition accuracy and provides a strong scientific basis for improving the volleyball players’ spike skills. Without interference from the right arm, the controller input and position tracking error will not fluctuate in 1 ≤ T ≤ 3 , the controller input is stable, and the output error is zero. Based on the above simulation analysis, it can be seen that the control method does not require the robot kinematics and dynamics model to generate any regression matrix when designing the controller. The controller is suitable for the performance tracking of humanoid robot arms.

Guest Editors’ Introduction: SBCCI 2020

The Symposium on Integrated Circuits and Systems Design (SBCCI) is an international forum dedicated to Integrated Circuits and Systems Design, Test and Electronic Design Automation (EDA), held annually in Brazil. The SBCCI has established itself as an important international forum for the presentation of advanced research results on leading-edge aspects of integrated circuits and systems design, such as analog circuits, mixed-signal and digital integrated circuits design, dedicated and reconfigurable architectures, EDA tools, design methods, embedded systems, SoC, and nanoarchitectures, as well as verification and test methods. This 33rd edition of SBCCI was initially planned to take place in Campinas, 100 km from São Paulo, but due to the COVID-19 pandemic, it was transformed into a virtual event.

Design and Performance Benchmarking of Hybrid Tunnel FET/STT-MTJ-Based Logic In-Memory Designs for Energy Efficiency

With CMOS technology scaling and increased short channel effects, spin-transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS-based logic-in-memory (LIM) designs consume significantly higher energy at scaled supply voltages. To enhance the energy efficiency of LIM circuit designs, this work proposes a hybrid tunnel FET (TFET)/MTJ-based digital circuit design approach at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathbf {DD}} = 0.3$ </tex-math></inline-formula> V. A Schmitt triggered pre-charge sense amplifier (ST-PCSA) with a strong feedback mechanism at the pull-down section is considered in TFET/MTJ-based LIM designs. The proposed LIM-MTJ designs are implemented using 20 nm TEFT technology and perpendicular anisotropy CoFeB/MgO/CoFeB MTJs. Two input and, or, xor logic gates, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times1$ </tex-math></inline-formula> multiplexer, 1-bit magnetic full adder (MFA), 4-bit magnetic ripple carry adder (RCA), and a simple 1-bit magnetic arithmetic and logical unit (M-ALU) are designed, exploring the proposed ST-PCSA-based hybrid TFET/MTJ logic. The proposed ST-PCSA-based hybrid TFET/MTJ LIM designs achieve ~47.2%–55.55% lower energy consumption in comparison with the PCSA-based TFET/MTJ LIM designs. Performance benchmarking with 20 nm FinFET designs demonstrates that the proposed TFET/MTJ LIM designs achieve 11.1%–25.9% lower energy consumption when compared with equivalent FinFET/MTJ-based LIM designs.