Subthreshold Slope Degradation Research Articles

Overcoming sub-threshold slope degradation in sub 10 nm technologies

Sub-threshold slope degradation is one of the difficulties preventing microchip scaling. This paper mainly concentrates on sub-threshold region of MOSFET and introduces the definition of sub-threshold swing (inverse of sub-threshold slope). The reason for this work is also told. Basing on ideal assumptions, the work considers 8 influence factors of sub-threshold. After comparison, high-k material, lower doping density, higher bias voltage and more ideal surface are good ways to solve the problem. Changing work function is conditional. The result is meaningful for further understanding of sub-threshold region and further scaling-down.

Overcoming sub-threshold slope degradation by the advances of TFETSs materials

With the scaling of devices in the past few decades, a lot of problems arise include short tunnel effect and significant power consumption, in which sub-threshold slope is a considerate factor. However, Sub-threshold Slope of MOSFET is limited to 60 mV/decade at room temperature due to Boltzmann Tyranny. TFETs (Tunnelling Field Effect Transistors) are the most promising field-effect transistors candidates owing to its potential to overcome sub-threshold slope degradation. This article illustrates the main principles of TFETs and explains how TFETs can overcome sub-threshold slope degradation through tunnelling effect. Furthermore, this article introduces the advances of TFETs materials to optimize devices performances.

Prospect for Overcoming Sub-threshold Slope Degradation with NC-FETs

Prospect for Overcoming Sub-threshold Slope Degradation with NC-FETs

9‐1: Evaluation of X‐ray Resistance of Submicron‐Size c‐Axis Aligned Crystalline‐Oxide Semiconductor

We have investigated the total ionizing dose effect by X‐rays, which is a degradation mode of a single transistor, to find the radiation resistance of oxide semiconductor large scale integrated circuit. At 3000 Gy corresponding to the absorbed dose for 30 years in a space environment, or more specifically, on a geostationary orbit, an oxide semiconductor field‐effect transistor showed a negative drift in threshold voltage of less than 300m V and substantially no degradation in subthreshold slope and mobility. After 60 hours from the irradiation, approximately 40% of the threshold voltage variation was recovered.

Analysis of Nitrogen-Doping Effect on Sub-Gap Density of States in a-IGZO TFTs by TCAD Simulation.

In this work, the impact of nitrogen doping (N-doping) on the distribution of sub-gap states in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) is qualitatively analyzed by technology computer-aided design (TCAD) simulation. According to the experimental characteristics, the numerical simulation results reveal that the interface trap states, bulk tail states, and deep-level sub-gap defect states originating from oxygen-vacancy- (Vo) related defects can be suppressed by an appropriate amount of N dopant. Correspondingly, the electrical properties and reliability of the a-IGZO TFTs are dramatically enhanced. In contrast, it is observed that the interfacial and deep-level sub-gap defects are increased when the a-IGZO TFT is doped with excess nitrogen, which results in the degeneration of the device’s performance and reliability. Moreover, it is found that tail-distributed acceptor-like N-related defects have been induced by excess N-doping, which is supported by the additional subthreshold slope degradation in the a-IGZO TFT.

Passivation of Solution-Processed a-IGZO Thin-Film Transistor by Solution Processable Zinc Porphyrin Self-Assembled Monolayer

Bottom-gate bottom contact amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) were fabricated using solution processing. The nonpassivated a-IGZO-TFTs exhibited a significant threshold voltage shift, large hysteresis in the current–voltage characteristics, and degradation in the subthreshold swing. TFTs’ performance degradation is due to the interaction of its back channel with adsorbed oxygen and water molecules in the ambient air. The hydroxy-phenyl zinc porphyrin (ZnP) self-assembled monolayer (SAM) was formed on TFTs’ back channel using a low-cost solution-based approach to passivate TFTs back channel. The passivated a-IGZO-TFTs exhibited enhanced electrical characteristics and improved stability compared with nonpassivated TFTs. Passivated TFTs presented significantly reduced hysteresis up to 87% and subthreshold slope degradation up to 71%. The passivated TFTs showed excellent stability under positive (20 V) and negative (−20 V) bias stress conducted for 5000 s.

Analytical drain current and performance evaluation for inversion type InGaAs gate-all-around MOSFET

This paper presents an analytical investigation of the drain current model for symmetric short channel InGaAs gate-all-around (GAA) MOSFETs valid from depletion to strong inversion using a continuous expression. The development of the core model is facilitated by the solution of the quasi-2D Poisson equation in the doped channel, accounting for interface trap defects and fixed oxide charges. Correction to short channel effects such as threshold voltage roll-off, drain induced barrier lowering, and subthreshold slope degradation is later introduced, complemented with channel length modulation, velocity saturation, and mobility degradation from surface roughness, leading to accurate mobile charge density for electrostatic capacitance–voltage and transport characterization. The effect of physical process parameters such as fin width, oxide thickness, and channel length scaling is thoroughly investigated in both on and off states of the transistor. The robustness of the model is reflected by the precise match with published experimental reports in the literature. An Ron of 1160 Ω μm is obtained from output characteristics and a switching efficiency improvement of 2.5 times is estimated by incorporating a high-κ dielectric into the GAA transistor. Numerical 3D simulations from TCAD corroborate the validity of the proposed model in all regions of operation.

Experimental Study on Short-Channel Effects in Double-Gate Silicon Carbide JFETs

Short-channel effects (SCEs) in double-gate silicon carbide junction field-effect transistors (JFETs) fully fabricated by ion implantation are experimentally investigated. The threshold voltage shift, drain-induced barrier lowering, and subthreshold slope degradation are clearly observed in the fabricated p- and n-JFETs. The SCEs are quantitatively evaluated by comparing with the theoretical values obtained by solving a 2-D Poisson equation, which shows good agreement with experiments. The dominant parameter for the SCEs in JFETs is the ratio of the channel length ( ${L}$ ) to the channel thickness ( ${a}$ ), and the device scaling rule to avoid the SCEs is estimated to be ${L}/{a} > {3}$ .

Study on interfacial trap location induced subthreshold slope degradation extracted by random telegraph noise for high-k/metal gate FinFET devices

In this work, constant voltage stress (CVS) induced interfacial trap and its effect on subthreshold slope (SS) degradation were studied for the first time by the random telegraph noise (RTN) technique. Part of the generated traps were located in the interfacial layer (IL) under CVS. Both the trap location and trapping number show a large impact on SS degradation, and it could be demonstrated by RTN. If the trap depths are similar, more traps cause more severe SS degradation. If the trap depths are different, shallow trap shows larger impact on SS degradation than that of deep trap even if the trapping charges of deep trap are more than that of shallow trap.

Advanced TCAD Simulation and Calibration of Gallium Oxide Vertical Transistor

In this paper, advanced β-Ga2O3 TCAD simulation parameters and methodologies are presented by calibrating simulation setup to vertical junctionless multi-gate transistor experimental data. Through careful calibration, several important β-Ga2O3 device physics are identified. The effects of compensation doping and incomplete ionization of dopants are investigated. Electron Philips unified carrier mobility (PhuMob) model, which can capture the temperature effect, is used. We also show that interfacial traps possibly play no role on the non-ideal sub-threshold slope (SS) and short channel effect is the major cause of SS degradation. The breakdown mechanism of the junctionless Ga2O3 transistor is also discussed and is shown to be limited by channel punch-through in off-state. The calibrated models match experimental Capacitance-Voltage (CV) and Current-Voltage (IV) well and can be used to predict the electrical performance of novel β-Ga2O3 devices.

Energy Filtering Effect at Source Contact on Ultra-Scaled MOSFETs

We postulate that in ultra-scaled Field Effect Transistors (FET), such as nanowires in sub7nm technology, the source contact will act as an energy filter and increase the effective temperature of carriers arriving at the channel barrier. This is due to the absence of inelastic scattering in the short source-contact-to-channel region. As a result, the Sub-threshold Slope (SS) will increase substantially. In this paper, we verify this energy filtering effect through numerical calculations and Technology ComputerAided-Design (TCAD) simulations calibrated to quantum solvers for electrostatics. It is found that SS degradation increases as the source metal workfunction increases. At 300K, in the nanowire simulated, SS increases from 94mV/dec to 109mV/dec for gate length, L G , = 10 nm and from 72mV/dec to 88mV/dec for L G = 15 nm, representing an increase of effective carrier temperature from 300K to more than 340K. The simulation result is also verified by including the Schroedinger equation (SE) for tunneling in TCAD simulation. It is also found that such an effect is worse at higher device temperature and disappears at cryogenic temperature.

Relationship of Channel and Surface Orientation to Mechanical and Electrical Stresses on N-Type FinFETs

The electric properties of a field-effect transistor not only depend on gate surface sidewall but also on channel orientation when applying channel stain engineering. The change of the gate surface and channel orientation through the rotated FinFETs provides the capability to compare the orientation dependence of performance and reliability. This study characterized the <100> and <110> channels of FinFETs on the same wafer under tensile and compressive stresses by cutting the wafer into rectangular silicon pieces and evaluated their piezoresistance coefficients. The piezoresistance coefficients of the <100> and <110> silicon under tensile and compressive stresses were first evaluated based on the current setup. Tensile stresses enhance the mobilities of both <100> and <110> channels, whereas compressive stresses degrade them. Electrical characterization revealed that the threshold voltage variation and drive current degradation of the {100} surface were significantly higher than those of {110} for positive bias temperature instability and hot carrier injection with equal gate and drain voltage (VG=VD). By contrast, insignificant difference is noted for the subthreshold slope degradation. These findings imply that a higher ratio of bulk defect trapping is generated by gate voltage on the <100> surface than that on the <110> surface.

Quantitative analysis of interface trap recovery caused by repetitive bending stress in flexible oxide thin-film transistors

We quantitatively characterized the thermal recovery process of flexible top-gate amorphous InGaZnO thin-film transistors stressed by repetitive mechanical bending. The interface trap density increases due to repetitive bending stress concentrated at the interface between the InGaZnO and Al2O3 layers near the source and drain electrodes. After 40 000 bending cycles, an increase in series resistance and subthreshold slope degradation is observed. Then, the restoration of the subthreshold slope is monitored over several hours at elevated temperatures. The threshold voltage remained nearly constant during this process. We propose a stretched exponential approach to the time-dependent subthreshold slope restoration to quantify the recovery of interface trap density at various temperatures. We present the method to extract the activation energy required for thermal relaxation of the interface trap sites generated by repetitive bending stress.

Pulse duration effect during pulsed gate-bias stress in a-InGaZnO thin film transistors

We investigated how the zero-voltage duration (0Vd) affects the tendency of degradation during pulsed gate bias stress in a-InGaZnO thin film transistors (TFTs). DC or pulsed negative bias illumination stress (NBIS) or positive bias stress (PBS) was applied to the TFTs for effective stress time of 4,000 s. While pulsed bias stress was being applied, stress-voltage duration (SVd) was set as either 10 s or 1 s per cycle, and 0Vd was varied from 100% to 1% of the SVd. During NBIS, degradation in both threshold voltage and sub-threshold slope became increasingly severe as 0Vd was shortened. However, during pulsed PBS, these trends were almost absent. These different tendencies may occur because the cause of each stress-induced degradation is fundamentally dissimilar; NBIS involves ionization of oxygen vacancies, whereas PBS involves electron trapping. The proposed mechanism was supported by additional bias stress tests on TFTs that had been immersed in H2O, where hydrogen became dominant factor causing the degradation.

Understanding hydrogen and nitrogen doping on active defects in amorphous In-Ga-Zn-O thin film transistors

This work analyses the physics of active trap states impacted by hydrogen (H) and nitrogen (N) dopings in amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and investigates their effects on the device performances under back-gate biasing. Based on numerical simulation and interpretation of the device transfer characteristics, it is concluded that the interface and bulk tail states, as well as the 2+ charge states (i.e., acceptors VO2+) related to oxygen vacancy (VO), are neutralized by the H/N dopants incorporation via an experimental plasma treatment. Moreover, the simulation reveals that an acceptor-like defect VOH has been induced by the H doping, to support the observed additional degradation of device subthreshold slope. Superior stability of the optimized a-IGZO TFTs under a proper amount of H/N doping is demonstrated by the decreased density of VO-related defects in simulation, where hole (VO0 donor) and electron trapping (Oi acceptor) occurs during the negative or positive bias stresses. This work benefit lies in an in-depth systematic understanding and exploration of the effects of the incorporation of the H and N dopants into the a-IGZO film for the TFTs improvement and optimization.

Effect of defect creation and migration on hump characteristics of a-InGaZnO thin film transistors under long-term drain bias stress with light illumination

We investigated the mechanism of formation of the hump that occurs in the current-voltage I-V characteristics of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) that are exposed to long-term drain bias stress under illumination. Transfer characteristics showed two-stage degradation under the stress. At the beginning of the stress, the I-V characteristics shifted in the negative direction with a degradation of subthreshold slope, but the hump phenomenon developed over time in the I-V characteristics. The development of the hump was related to creation of defects, especially ionized oxygen vacancies which act as shallow donor-like states near the conduction-band minimum in a-IGZO. To further investigate the hump phenomenon we measured a capacitance-voltage C-V curve and performed two-dimensional device simulation. Stretched-out C-V for the gate-to-drain capacitance and simulated electric field distribution which exhibited large electric field near the drain side of TFT indicated that VO2+ were generated near the drain side of TFT, but the hump was not induced when VO2+ only existed near the drain side. Therefore, the degradation behavior under DBITS occurred because VO2+ were created near the drain side, then were migrated to the source side of the TFT.

Electrical characterization and reliability of submicron SOI CMOS technology in the extended temperature range (to 300 °C)

I-V characteristics and reliability parameters for the set of hardened SOI MOSFET's with special layouts and tungsten metallization to provide additional thermal tolerance for high-temperature SOI CMOS IC's are investigated in the temperature range up to 300°C. The reliability aspects under test for MOSFET's are threshold voltage shift, subthreshold slope and mobility degradation, gate leakage current rise; for tungsten metallization (contacts, conductor lines and vias) I-T and R-T characteristics, failure time. The SOI MOSFET standard compact SPICE model BSIMSOI with traditional temperature limit of 150°C is modified to be used for CMOS IC simulation in the extended temperature range up to 300°C. The results indicate that the 0.5–0.18μm SOI MOSFET's with tungsten metallization have stable electrical behavior that makes them possible to be used during implementation of HT CMOS IC's (to 300°C).

A Novel Tunnel FET Design Through Adaptive Bandgap Engineering With Constant Sub-Threshold Slope Over 5 Decades of Current and High $\text{I}_{\mathrm {ON}}/\text{I}_{\mathrm {OFF}}$ Ratio

In this letter, a novel hetero-stacked TFET (HS-TFET) is experimentally demonstrated and optimized for the first time, which can effectively suppress the sub-threshold slope (SS) degradation without leakage current increase through self-adaptively current replenishing with bandgap engineering, greatly alleviating the critical issue of high average SS in conventional TFETs. Based on CMOS-compatible technology, the fabricated HS-TFETs of vertically stacked Si-Si1–xGex source can experimentally achieve superior performance with nearly constant SS over five decades of drain current, high $I_{{{\mathrm{\scriptscriptstyle ON}}}}$ ( $\sim 14\mu \text{A}/\mu \text{m}$ @ $V_{\mathrm {DS}}=-1$ V), and large $I_{{{\mathrm{\scriptscriptstyle ON}}}}/I_{{{\mathrm{\scriptscriptstyle OFF}}}}$ ratio ( $\sim 10^{7})$ . The proposed device with high process compatibility shows great potentials for future ultra-low power applications.

Amended Electric Field Distribution: A Reliable Technique for Electrical Performance Improvement in Nano scale SOI MOSFETs

To achieve reliable transistors, we propose a new silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) with an amended electric field in the channel for improved electrical and thermal performance, with an emphasis on current leakage improvement. The amended electric field leads to lower electric field crowding and thereby we assume enhanced reliability, leakage current, gate-induced drain leakage (GIDL), and electron temperature. To modify the electric field distribution, an additional rectangular metal region (RMR) is utilized in the buried oxide of the SOI MOSFET. The location and dimensions of the RMR have been carefully optimized to achieve the best results. The electrical, thermal, and radiofrequency characteristics of the proposed structure were analyzed using two-dimensional (2-D) numerical simulations and compared with the characteristics of the conventional, fully depleted SOI MOSFET (C-SOI). Also, critical short-channel effects (SCEs) such as threshold voltage, drain-induced barrier lowering (DIBL), subthreshold slope degradation, hot-carrier effect, GIDL, and leakage power consumption are improved. According to the results obtained, the proposed nano SOI MOSFET is a reliable device, especially for use in low-power and high-temperature applications.

Effect of Light Intensity and Wavelength on a-Ingazno Thin Film Transistors Under Negative Bias Illumination Stress

Amorphous InGaZnO (a-IGZO) has excellent properties such as high on/off ratio, good uniformity, and low processing temperature, so they are promising channel material for thin film transistors (TFTs). Instability mechanism of a-IGZO TFTs depending on environmental effects, bias, temperature and illumination stress was widely investigated and reported. Especially in the case of negative bias stress, degradation is accelerated under illumination and many studies have been done to clarify the causes. However, the effects of wavelength and intensity of light during negative bias stress under illumination stress (NBIS) have not been fully explained yet. Transfer characteristics of a-IGZO TFTs with back channel etch structure were measured after NBIS is applied. Gate voltage of -40 V was applied at 90 °C for 4000 s while drain and source were grounded. Illumination from white LED was passed through blue, green and red color filters which have peak wavelengths of 450 nm, 530 nm and 700 nm, respectively. To verify the relationship between intensity of light and degradation, measurements were done with various intensities of light. Severe negative shifts in transfer curve was shown under NBIS with blue light, while relatively little shifts were shown with green, red light and in darkness (Fig. 1). Apparent degradation in subthreshold slope was observed with blue light, which represents the creation of sub-gap states (Fig. 1d). Shifts in Vth as a function of stress time were extracted with various illumination conditions (Fig.2). The intensities of illumination were 4500 lux for white and 100 lux for blue, green and red light. Despite of much lower intensity compared to that of white light, blue light induced comparable amount of Vth shifts with that of white light; Vthshifts after 4000 s of stress were about -17.7 V for white and -16.3 V for blue light, but were only about -1.0 V for green light, -0.8 V for red light and -0.7 V for in darkness. To clarify the effect of intensity in blue light, we adjusted the intensity as 100, 50, 25, 12 and 6 lux with the same stress condition. Amount of Vth shifts were not significantly altered until the illumination was reduced to 25 lux, but started to show drastic decrease below 25 lux (Fig. 3a). It indicates that threshold intensity of illumination and saturation phenomenon exist in NBIS induced degradation of IGZO TFTs. Measurements were repeated at 60 °C and Vthshifts as a function of intensity was plotted with different temperature condition (Fig. 3b). Saturation phenomenon started at higher intensity of light (50 lux) for low temperature, which can be interpreted in terms of activation energy. In this work, we investigated the effect of wavelength and intensity of light in degradation of a-IGZO TFTs induced by NBIS. We discovered the existence of threshold light intensity and observed saturated behavior in Vth shifts under NBIS with respect to intensity. We will explain degradation mechanism in NBIS depending on wavelength and introduce new instability mechanism related to intensity of light. Figure 1