Pulse duration effect during pulsed gate-bias stress in a-InGaZnO thin film transistors

Abstract

We investigated how the zero-voltage duration (0Vd) affects the tendency of degradation during pulsed gate bias stress in a-InGaZnO thin film transistors (TFTs). DC or pulsed negative bias illumination stress (NBIS) or positive bias stress (PBS) was applied to the TFTs for effective stress time of 4,000 s. While pulsed bias stress was being applied, stress-voltage duration (SVd) was set as either 10 s or 1 s per cycle, and 0Vd was varied from 100% to 1% of the SVd. During NBIS, degradation in both threshold voltage and sub-threshold slope became increasingly severe as 0Vd was shortened. However, during pulsed PBS, these trends were almost absent. These different tendencies may occur because the cause of each stress-induced degradation is fundamentally dissimilar; NBIS involves ionization of oxygen vacancies, whereas PBS involves electron trapping. The proposed mechanism was supported by additional bias stress tests on TFTs that had been immersed in H2O, where hydrogen became dominant factor causing the degradation.