Energy Filtering Effect at Source Contact on Ultra-Scaled MOSFETs

Johan Saltin,Philip H W Leong,Hiu Yung Wong,Nguyen Cong Dao

doi:10.1109/jeds.2020.2981251

Abstract

We postulate that in ultra-scaled Field Effect Transistors (FET), such as nanowires in sub7nm technology, the source contact will act as an energy filter and increase the effective temperature of carriers arriving at the channel barrier. This is due to the absence of inelastic scattering in the short source-contact-to-channel region. As a result, the Sub-threshold Slope (SS) will increase substantially. In this paper, we verify this energy filtering effect through numerical calculations and Technology ComputerAided-Design (TCAD) simulations calibrated to quantum solvers for electrostatics. It is found that SS degradation increases as the source metal workfunction increases. At 300K, in the nanowire simulated, SS increases from 94mV/dec to 109mV/dec for gate length, L G , = 10 nm and from 72mV/dec to 88mV/dec for L G = 15 nm, representing an increase of effective carrier temperature from 300K to more than 340K. The simulation result is also verified by including the Schroedinger equation (SE) for tunneling in TCAD simulation. It is also found that such an effect is worse at higher device temperature and disappears at cryogenic temperature.

Highlights

One of the main goals in transistor scaling is to increase the drain current ON/OFF ratio (ION/IOFF) [1] so that the transistor is a close approximation to an ideal switch
By assuming the ballistic transport and non-ballistic transport cases have the same n and since the non-ballistic case has device temperature equals to the ambient temperature (300K in this case), Teff is found by considering the ratio of Sub-threshold Slope (SS) of both cases
We report that in ultra-scaled Field Effect Transistors (FET), SS will be larger than expected due to the energy filtering effect in the source contact

Summary

Introduction

One of the main goals in transistor scaling is to increase the drain current ON/OFF ratio (ION/IOFF) [1] so that the transistor is a close approximation to an ideal switch. The smaller the SS, the more the drain current is reduced as the gate voltage is decreased, and so lower leakage can be achieved for a given ION. Novel transistors based on different mechanisms such as the Tunnel Field Effect Transistor (TFET) [5] and Negative Capacitance FET (NCFET) [6] have been proposed to reduce SS below 60 mV/dec at 300K. Such devices usually either have low ION or are difficult to optimize

Results

Discussion

Conclusion