Study on interfacial trap location induced subthreshold slope degradation extracted by random telegraph noise for high-k/metal gate FinFET devices

Abstract

In this work, constant voltage stress (CVS) induced interfacial trap and its effect on subthreshold slope (SS) degradation were studied for the first time by the random telegraph noise (RTN) technique. Part of the generated traps were located in the interfacial layer (IL) under CVS. Both the trap location and trapping number show a large impact on SS degradation, and it could be demonstrated by RTN. If the trap depths are similar, more traps cause more severe SS degradation. If the trap depths are different, shallow trap shows larger impact on SS degradation than that of deep trap even if the trapping charges of deep trap are more than that of shallow trap.