Abstract
In this work, we propose a more accurate description of the interface trap in the MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> field-effect transistor using a quantum-mechanical modeling framework. Introducing an interface trap based on tight-binding parameter substitution at an atomic site is found to be a more effective way to include its effect on the device electrostatics and the carrier transport. Further, lower energy interface traps from conduction band are found to significantly impact the device performance, with severe degradation in subthreshold slope and ON-current. Our proposed model reveals that charge trapping in the interface trap causes substantial degradation in the drive current for high gate biases, whereas source-to-drain tunneling through trap limits the performance for low gate biases.
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