Decoder Circuit Research Articles

High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme

A mixed-logic design scheme utilizing pass-transistor logic (PTL) and dual-value logic (DVL) in combination with static CMOS logic for decoders in SRAMs is proposed. By using of the mixed-logic circuit, new n-Transistor (T) NAND/AND structures were provided for decoders, while achieving fewer transistors, faster speed, lower power dissipation as compared to traditional circuits, and having full-swing capability and good noise immunity. Experiments were conducted using TSMC 28 nm process for mixed-logic decoders, and the results show the superiority in terms of propagation delay and power dissipation, compared to the conventional corresponding circuits. A mixed-logic 2-4 decoder exhibits 36 % reduction in propagation delay and 10 % improvement in power dissipation; A mixed-logic 3-8 decoder exhibits 27 % reduction in propagation delay and 5.5 % improvement in power dissipation; While, A mixed-logic 4-16 decoder exhibits 30 % reduction in propagation delay and 5 % improvement in power dissipation; As well, A mixed-logic 5-32 decoder exhibits 34 % reduction in propagation delay and 6.3 % improvement in power dissipation.

Splicable random windowing row selection circuit for large array CMOS image sensor

This paper presents a splicable random window row selection circuit applied to large array CMOS image sensors (CIS) for exposure and readout of certain pixel rows in large array CIS. The row selection circuit consists of coarse decoding and fine decoding circuits, utilizing two-stage address selection operations for precise row selection. The coarse decoding address is used to enable the splicing module of the large array CIS, while the fine decoding address is used to enable a specific row in the selected splicing module. This solves the problem of output redundancy caused by the same row address bits in different splicing blocks in the large array CIS. The paper introduces an improved bilateral driving technique, reducing the transmission delay to 1/4 of single-sided driving while ensuring timing consistency with coarse decoding circuits. This technique is applied to large arrays of CIS with dimensions of 8520 × 9448, successfully realizing the random window function.

Design of unbalanced 9:2 ternary encoder and 2:9 ternary decoder circuits in resistive random access memory and carbon nanotube field effect transistor technology

SummaryMultivalued logic (MVL) offers higher information density as compared with binary logic systems for an equal number of digits. In a ternary microprocessor, memory access is the most time‐ and power‐consuming action. In order to design a ternary computer, the possibilities for designing ternary encoders and decoders must be examined. This paper presents the designs of 9:2 unbalanced ternary encoder (TENC) and 2:9 unbalanced ternary line address decoder (TDEC) based on novel designs of standard ternary inverter (STI), ternary NAND (TNAND), and ternary NOR (TNOR) logic gates using resistive random‐access memory (RRAM) and carbon nanotube field effect transistor (CNTFET) technology. The simulation results indicate an improvement in performance parameters such as power consumption, delay, power–delay product (PDP), and component count of the proposed circuits in comparison with the different existing counterparts. Moreover, a detailed analysis is carried out on the impact of different process, voltage, and temperature (PVT) variations on the performance metrics, including propagation delay, power consumption, and PDP of the 9:2 unbalanced ternary encoder and 2:9 unbalanced ternary line address decoder. The proposed ternary encoder circuit shows an improvement of 62% in delay, 71% in power consumption, 88.6% improvement in PDP, and 53% reduction in CNTFET count, whereas the ternary decoder circuit exhibits an improvement of 6.6% and 94% in delay and 43% and 94% improvement in power consumption, respectively. Moreover, the CNTFET count is reduced by 16.07% and 46%.

Design of Reversible Quantum Vigenere Cryptographic Cipher in QCA and IBMQ Platforms for Secure Nanocommunication

Using cryptography correctly is crucial in the current situation to safeguard data and ensure data security during data transfer. In this digital era, messages must be appropriately encrypted and decoded to prevent data misuse and ensure its accessibility to the intended recipient. Conventional cryptography techniques mostly depend on the mathematical intricacy of the encoding functions and the shared key. One such encoding approach that we may take into consideration is the Vigenere cipher algorithm. In this study, we want to apply this strategy utilizing reversible logic with the assistance of two helpful tools, namely, IBM Quantum (IBMQ) and QCADesigner. The encoder and decoder circuits for the Vigenere cipher are therefore proposed in this work in QCADesigner by utilizing Peres and DG gates in quantum-dot cellular automata (QCA) that consist of a single layer with 42 cells for encryption and 47 cells for decryption. The proposed circuit outperforms the existing ones concerning area, cell count and latency. Given that the layouts’ energy consumption is assessed, it is guaranteed that the QCA nanodevice might serve as a stand-in platform for the creation of reversible circuits. The same simulation outcome was also obtained while building the identical circuits in a quantum presentation using IBMQ. The two applications are closely connected and both rely on quantum concepts. The outcomes are therefore verified for each of the two situations. The reversible Vigenere cipher technique enhances data security. Further sophisticated low-power nanoscale lossless nanocommunication architecture may be created with the help of the suggested circuits.

Design of an IMI optical 2 × 4 decoder circuit based on square disk resonators.

This paper presents the design of a 2×4 decoder that was developed by using the finite element method (FEM) in conjunction with the COMSOL version 5.5 software. Insulator-metal-insulator (IMI) waveguides with four substructures were used in the fabrication of the plasmonic decoder. Gold is used as a conducting material. Thisis a challenge for us, while Teflon is used as a dielectric material in the fabrication process. The dimensions of thispart are 1090nm by 400nm. At an operating wavelength of 1550nm, the transmission threshold (T t h r e s h o l d ) of this scheme has been determined to be 10%. In order to assess the effectiveness of the plasmonic decoder, it is recommended that the modulation depth (MD), contrast ratio (CR), and insertion loss (IL) parameters be carried out. Both the highest values of CR and MD are 12.33 decibels, and the maximum value of MD is 99.96%. It is because of these qualities that this work is distinguished from earlier works.

Secure nano-communication framework using RSCV cryptographic circuit in IBM Q

In the cryptographic domain, quantum and its real-time hardware simulation make it easier to secure data during communication. Here, using quantum logic, a unique encryption technique called Reversible select, cross, and variation (RSCV) encryption and decryption, which involves swapping input data halves, is shown. In this article using IBM Q, we created a cryptographic encoder and decoder circuit design utilizing various quantum gates. Based on the encoder/decoder circuit, a simple nanocommunication framework is proposed. Further, to explore the application of the noise model, how to utilize this model to create noisy replicas of these quantum circuits to research the impacts of noise that occur for actual device output is shown. To reduce measurement mistakes, measurement calibration is performed using qiskit ignis model. Preparing all 2n basis input states and calculating the likelihood of counting in the other basis states are the key concepts. The percentage improvement we achieved is 40%, 30%, and 30%, respectively, compared to earlier ones, in RSCV encryption, decryption, and RSCV cryptographic communication architecture for fake provider noise error model. It is feasible to adjust the average outcomes of an additional interesting experiment using these calibrations.

Ternary encoder and decoder designs in RRAM and CNTFET technologies

A possible way for the very large scale integration (VLSI) industry to keep up with the pace of high density, computational capability, and energy efficiency is to look into some technologies ahead of binary logic. In recent years, multiple-valued logic (MVL) has caught the notable attention of digital system designers. The carbon nanotube field effect transistor (CNTFET) has been exclusively used for the implementation of MVL circuits. Resistive random-access memory (RRAM) offers a very durable option for executing the MVL due to its capability of storing various resistance states in one cell. In this paper, a ternary 9:2 encoder and a ternary 2:9 decoder have been designed and simulated using the proposed RRAM-based ternary logic gates with standard 32nm CNTFETs. In comparison to other ternary circuits in the literature, the proposed CNTFET RRAM-based ternary logic circuits show less power consumption, delay, and power delay product (PDP). The power of the CNTFET RRAM-based proposed ternary inverter (TI), ternary NAND (TNAND), and ternary NOR (TNOR) is 32.78%, 51.48%, and 24.14% less than the lowest power of the other designs under consideration. The PVT variations and reliability of the proposed encoder and decoder circuits have also been studied.

PWM-to-message signal decoder circuit system based on opto-electronic devices and their PPC characteristics

PWM-to-message signal decoder circuit system based on opto-electronic devices and their PPC characteristics

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

Kerr effect based optical switching for the assessment of all-optical sequence generator and decoder circuits

Abstract The sequence generator and decoders are used for noise analysis, signal propagation, data processing, and bit error rate analysis. The semiconductor and modern electronic components are facing challenges in terms of processing speed and data rates. However, by using photons rather than electrons as the information carriers, these difficulties can be reduced. Photonic devices attained the operating speed in the regime of terahertz, but sit back due to the diffraction limit, which can be overcome by employing plasmon-based devices or all-optical devices. This work presents a numerical investigation of metal-insulator-metal (MIM) plasmonic waveguides based two-bit sequence generator (SG) and decoder. The structure of SG and decoder circuits are designed within the footprints of 86 × 9 and 140 × 9 µm, by cascading one power splitter (PS) and four Mach-Zehnder interferometers (MZIs), and two PS and five MZI, respectively. To design the MZI, the optimization of the S-bend waveguide, the coupling length of the power splitter, and the length of the interferometric arm are done by recording the output power. The highest extinction ratio of 22.1 dB is attained at the coupling and interferometric arm lengths of 1.5 µm and 5 µm, respectively. The propagation of the optical signal through the structure of SG is observed by using a two-dimensional finite difference time domain method-based tool.

High-performance ternary designs using graphene nanoribbon transistors

Considering the issues emerging because of shrinking silicon field effect transistors (FETs), various post-silicon, post-binary logics are investigated by the researchers. The design of ternary schematics utilizing graphene nanoribbon FET (GNRFET) circuits is one alternate option. Since different threshold voltages are obtained by employing GNRFETs by varying its physical dimension, GNRFET is an ideal option for designing ternary circuits. The ternary circuit designs such as adder, subtractor and multiplier using GNRFETs are proposed in this study. These designs are developed using the ternary based decoder circuit. The proposed circuits are developed and executed in Synopsys based HSPICE simulator for functional verification. Additionally, the performances such as delay, power, power-delay-product (PDP) and energy-delay-product (EDP) of the proposed circuits are investigated and compared to CNTFET based ternary designs. The GNRFET ternary designs improved the performance on an average up to 30.96% than the CNTFET based designs.

Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”

This paper comments on the some mistakes which have been observed in Tripathi et al. (2023) [1]. We have specifically pointed out the following mistakes of Tripathi et al. (2023) [1].i) Presented (41, 32) SEC-DAEC-TAEC H-matrix in Fig. 3 of Tripathi et al. (2023) [1].ii) Presented error detection and correction coverage in Table 6 of Tripathi et al. (2023) [1].The corrected versions of the above mentioned mistakes have been presented in this paper. Also the FPGA-based synthesis result of corrected encoder and decoder circuits based on the corrected (41, 32) H-matrix have been presented here.

Cost-effective architecture of decoder circuits and futuristic scope in the era of nano-computing

Cost-effective architecture of decoder circuits and futuristic scope in the era of nano-computing

Nano‐scale design of full adder and full subtractor using reversible logic based decoder circuit in quantum‐dot cellular automata

AbstractThis paper presents a reversible nano‐scale decoder circuit. The decoder is designed by utilizing the new quantum‐dot cellular automata (QCA) format of the QCA1 gate. This QCA1 gate provides 34.25% less cell count with 54.37% less area than the best existing designs. Thus, the proposed QCA1 gate provides less area considering the best existing state‐of‐the‐art plans. The IBMQ‐based quantum realization of the QCA1 gate is also illustrated. The reversible full adder and subtractor circuits by employing the proposed decoder are likewise explored in this paper. A four‐input reversible OR‐gate is structured and concatenates with a decoder circuit to frame the circuit for full adder and subtractor. The energy dissipation by these QCA circuits is assessed to build up that QCA is an attractive option to CMOS for realizing reversible logic designs. The implemented results are compared with the truth table to ensure operational accuracy. The planned circuits can be utilized to structure reversible designs for nano‐communication.

Non-Volatile Nano-Electro-Mechanical Switches and Hybrid Circuits in a 16 nm CMOS Back-End-of-Line Process

Reprogrammable non-volatile (NV) vertically-oriented nano-electro-mechanical (NEM) switches with a compact footprint are successfully implemented using multiple back-end-of-line (BEOL) interconnect layers of a standard 16-nm CMOS process technology, with no additional lithography steps. A compact decoder circuit comprising an array of these reconfigurable interconnects is successfully demonstrated. As the minimum metal pitch decreases with each new manufacturing process generation, hybrid CMOS+NEM technology becomes increasingly attractive for ultra-low-power reconfigurable computing applications.

Novel qutrit circuit design for multiplexer, De-multiplexer, and decoder

Designing conventional circuits present many challenges, including minimizing internal power dissipation. An approach to overcoming this problem is utilizing quantum technology, which has attracted significant attention as an alternative to Nanoscale CMOS technology. The reduction of energy dissipation makes quantum circuits an up-and-coming emerging technology. Ternary logic can potentially diminish the quantum circuit width, which is currently a limitation in quantum technologies. Using qutrit instead of qubit could play an essential role in the future of quantum computing. First, we propose two approaches for quantum ternary decoder circuit in this context. Then, we propose a quantum ternary multiplexer and quantum ternary demultiplexer to exploit the constructed quantum ternary decoder circuit. Techniques to achieve lower quantum cost are of importance. We considered two types of circuits, one in which the output states are always restored to the initial input states and the other in which the states of the output are irrelevant. We compare the proposed quantum ternary circuits with their existing counterparts and present the improvements. It is possible to realize the proposed designs using macro-level ternary gates that are based on the ion-trap realizable ternary 2-qutrit Muthukrishnan–Stroud and 1-qutrit permutation gates.

Energy consumption modeling and analysis for short-reach optical transmissions using irregular LDPC codes.

As the transmission rate of data center (DC) related short-reach optical transmissions quickly increases to keep up with internet services' data demand pace, advanced FEC technology starts to establish its key role in short reach optical transmission systems. Coding strategy using Quasi-Cyclic LDPC (QC-LDPC) codes with hard-decision (HD) decoders stands out due to its excellent error correction ability and simple hardware implementation. Meanwhile, with the introduction of green communication concept and increasingly extensive applications of DC, energy consumption of short-reach links has become an urgent problem to be studied. Based on tanner-graph, energy consumption models of regular LDPC codes' HD decoding circuits over AWGN channel have been proposed. In this work, for the first time, we introduce energy consumption of optical transmitters and characteristics of short reach optical channels into energy consumption modeling. Besides, probability distributions of flipping operation as well as bit errors during irregular QC-LDPC codes' HD decoding iterations are analytically derived using density evolution algorithm. Based on our proposed model and post-layout circuit simulation, systems' total power when using four QC-LDPC codes in IEEE and 3GPP with Gallager A/B decoders together with the case of using no FEC are analyzed in two typical scenarios. Numerical results show that, in short range scenario with slight bandwidth limit, uncoded strategy is much more energy-saving than all adopted LDPC-coded strategies in 50Gbaud OOK and 25Gbaud PAM4 transmissions. While in severely band-limited case when FEC is necessary, a tradeoff between energy consumption of transmitters and decoders occurs in 70Gbaud OOK and 35Gbaud PAM4 transmissions. Besides, LDPC codes with longer length at similar rate are proved to consume less power for their better error correction ability. And in long range scenario, power differences among coding strategies grow significantly when pre-bit error rate (BER) approaches their error correction threshold, reflecting the great influence of error correction threshold on the energy consumption of LDPC decoders. Among all adopted coding strategies, a (19200, 15872) LDPC code with Gallager B decoder consumes minimum power in both two scenarios. However, it is also found that decoding algorithm minimizing the total power differs at different pre-BER if we concentrate on decoding algorithm, justifying the significance of our modeling in minimizing system energy consumption.

Cost-effective Programmable Logic Arrays Using Multilayer Structures of Decoders in QCA Framework

The emerging nanotechnology paradigm, Quantum Dot Cellular Automata (QCA) in particular, is gaining a wide recognition due to its high speed, nano feature size and considerably low power consumption. The QCA architecture not only provide potential alternative for Complementary Metal Oxide Semiconductor (CMOS) circuits but its multilayer topology facilitates an added benefit of cost efficacy and immunity towards random interference. Moreover, design of programmable logic devices in QCA is vital to promote the multi-utility and resiliency of the computing circuits. This paper presents the multilayer designs of 2×4 and 3×8 decoder circuits in QCA framework with 55.1% and 51.17% better cost efficiency respectively, over the earlier reported designs. The presented 3×8 decoder circuit is further utilized to implement Programmable Logic Array (PLA) to realize Boolean functions of adder and subtractor. The presented circuits are cost effective and showcase the significance of programmable devices in nano-computing.

A novel design approach for T‐XOR gate in ternary quantum‐dot cellular automata circuits

AbstractReducing the size of transistors to nano‐dimensions has brought new problems and challenges to the semiconductor field‐effect transistor industry. Therefore, quantum cells are considered as an alternative technology to solve these problems. The efforts of the past few years on the earth of nano‐electronics circuits have focused more on minimizing the cost of hardware by processing more than two values per basic action. In this paper, for the first time, the ternary XOR circuit has been designed and simulated in ternary quantum cells (TQCA) technologies. The proposed ternary XOR‐based on TQCA with 369 cells, area‐delay cost (m2 − scc) is 136.76, power equal to 1704.7 × 10−20 J equivalent to 106.4 eV, area 0.074128 μm2, and a delay of 1.25 clock was designed and simulated for validation with TQCAsim software. In addition, the ternary decoder circuit was simulated with 14 cells, cost (m2 − scc) is 0.0339, area 0.0021 μm2, and delay of one clock cycle. The comparison indicates that TQCA technology has unique behaviors and advantages in various criteria such as low power consumption, delay reduction, reduction of occupied space, and a significant increase in working frequency.