Splicable random windowing row selection circuit for large array CMOS image sensor

Abstract

This paper presents a splicable random window row selection circuit applied to large array CMOS image sensors (CIS) for exposure and readout of certain pixel rows in large array CIS. The row selection circuit consists of coarse decoding and fine decoding circuits, utilizing two-stage address selection operations for precise row selection. The coarse decoding address is used to enable the splicing module of the large array CIS, while the fine decoding address is used to enable a specific row in the selected splicing module. This solves the problem of output redundancy caused by the same row address bits in different splicing blocks in the large array CIS. The paper introduces an improved bilateral driving technique, reducing the transmission delay to 1/4 of single-sided driving while ensuring timing consistency with coarse decoding circuits. This technique is applied to large arrays of CIS with dimensions of 8520 × 9448, successfully realizing the random window function.