High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme

Abstract

A mixed-logic design scheme utilizing pass-transistor logic (PTL) and dual-value logic (DVL) in combination with static CMOS logic for decoders in SRAMs is proposed. By using of the mixed-logic circuit, new n-Transistor (T) NAND/AND structures were provided for decoders, while achieving fewer transistors, faster speed, lower power dissipation as compared to traditional circuits, and having full-swing capability and good noise immunity. Experiments were conducted using TSMC 28 nm process for mixed-logic decoders, and the results show the superiority in terms of propagation delay and power dissipation, compared to the conventional corresponding circuits. A mixed-logic 2-4 decoder exhibits 36 % reduction in propagation delay and 10 % improvement in power dissipation; A mixed-logic 3-8 decoder exhibits 27 % reduction in propagation delay and 5.5 % improvement in power dissipation; While, A mixed-logic 4-16 decoder exhibits 30 % reduction in propagation delay and 5 % improvement in power dissipation; As well, A mixed-logic 5-32 decoder exhibits 34 % reduction in propagation delay and 6.3 % improvement in power dissipation.