High-performance ternary designs using graphene nanoribbon transistors

Abstract

Considering the issues emerging because of shrinking silicon field effect transistors (FETs), various post-silicon, post-binary logics are investigated by the researchers. The design of ternary schematics utilizing graphene nanoribbon FET (GNRFET) circuits is one alternate option. Since different threshold voltages are obtained by employing GNRFETs by varying its physical dimension, GNRFET is an ideal option for designing ternary circuits. The ternary circuit designs such as adder, subtractor and multiplier using GNRFETs are proposed in this study. These designs are developed using the ternary based decoder circuit. The proposed circuits are developed and executed in Synopsys based HSPICE simulator for functional verification. Additionally, the performances such as delay, power, power-delay-product (PDP) and energy-delay-product (EDP) of the proposed circuits are investigated and compared to CNTFET based ternary designs. The GNRFET ternary designs improved the performance on an average up to 30.96% than the CNTFET based designs.