DC Power Consumption Research Articles

A Compact V-Band Temperature Compensation Low-Noise Amplifier in a 130 nm SiGe BiCMOS Process.

This paper presents a compact V-band low-noise amplifier (LNA) featuring temperature compensation, implemented in a 130 nm SiGe BiCMOS process. A negative temperature coefficient bias circuit generates an adaptive current for temperature compensation, enhancing the LNA's temperature robustness. A T-type inductive network is employed to establish two dominant poles at different frequencies, significantly broadening the amplifier's bandwidth. Over the wide temperature range of -55 °C to 85 °C, the LNA prototype exhibits a gain variation of less than 1.5 dB at test frequencies from 40 GHz to 65 GHz, corresponding to a temperature coefficient of 0.01 dB/°C. At -55 °C, 25 °C, and 85 °C, the measured peak gains are 25.5 dB, 25 dB, and 24.4 dB, respectively, with minimum noise figures (NF) of 3.0 dB, 3.5 dB, and 4.2 dB, and DC power consumptions of 22.3 mW, 27.6 mW, and 34.4 mW. Moreover, the total silicon area of the LNA chip is 0.37 mm2, including all test pads, while the core area is only 0.09 mm2.

Investigations into optimum non‐periodic bursts scheme in radar pulse train designed for fixed‐wing drone detections by multi‐function radar

AbstractDrone surveillance with multi‐function radar (MFR) can benefit a lot from the careful radar pulse train organisation into dedicated sub‐RPTs serving particular needs of tasks. In contemporary scenarios of MFR applications, where navigation, search and rescue, and natural environment safeguarding are to be shared, of particular importance is a case where airborne small drone detection radar performs other tasks concurrently. Resource sharing within the radar unit is based on variables and unpredictable circumstances, leading to strains in resources in MFR. Consequently, such constraints limit MFR functioning with optimal drone sensitivity for its own sake. To ensure a high quality of radar services performed quickly, with a low DC power consumption, the task sharing approach by the common MFR platform, non‐periodic bursts emission of radar pulse energy has gained our major attention. At the same time, it was assumed that bursts feature periodic time intervals between radar pulses, which is a favourable circumstance in the control and implementation of signal processing. Each sub‐RPTs is designed to cope with particular detection tasks. One to four linear polarisations (VV, VH, HV, HH) are activated. The focus of the investigation was on the radar emitting a few thousand pulses per second, but only a few 10 pulses per second were expected to be required to detect small airborne drones. The core of the research study was the optimisation process of the scheme operating with 4 to 16 pulse bursts optimised for drone detection with a modest use of resources at MFR. While performing several activities, the X‐band MFR platform called ENAVI was developed in‐house. The proposed non‐periodic burst scheme optimisation approach was validated with in‐field tests with the ENAVI radar model. The in‐air target was a 3‐metre fixed‐wing drone having low RCS and flying at different altitudes with a speed close to 200 km/h. The radar antenna was a 26 dBi low‐profile dual‐polarisation array making it feasible to detect drones remaining a few degrees off the antenna breadboard direction. A very high likelihood of detection of drones from a few kilometres distance was demonstrated within one second. The authors present the effectiveness of the cell‐averaging technique which proved to correctly detect drones within a 7‐km range, and how MFR radar echoes can be used for basic weather surveillance. One vertical VV polarisation was used for drone detection and two VV and VH polarisations for weather observation. Weather radar capabilities were examined against heavy rain clouds imposing a hazard to the safety of drone flights.

A 30-60 GHz Broadband Low LO-Drive Down-Conversion Mixer with Active IF Balun in 65 nm CMOS Technology.

A 30~60 GHz broadband down-conversion mixer driven by low local oscillator (LO) power is presented. The down-conversion mixer utilizes an input signal coupling technique based on the Marchand balun to achieve broadband operation and achieves low LO power drive and low DC power consumption through the use of a weak inversion bias with Gilbert switching devices. The broadband conversion of single-ended to differential signals is achieved using the Marchand balun with compensation lines, and an equivalent circuit analysis is performed. For the intermediate frequency (IF) output, a self-biased IF trans-impedance amplifier with current reusing and an active IF balun structure are used to achieve signal amplification and single-ended signal output. Test results show that the proposed mixer achieves a conversion gain of -1.2 to 6.4 dB in an IF output bandwidth of 0.1 to 5 GHz at radio frequency (RF) input frequencies of 30 to 60 GHz and LO driving power of -10 dBm. The DC power consumption of the core mixing unit of the proposed mixer is 4.8 mW, and the DC power consumption including the IF amplifier is 28.3 mW. The proposed mixer uses a 65 nm CMOS technology with a chip area of 0.26 mm2.

Research on Fixed-Slope On-Chip Soft-Start Method Applied to Buck DC–DC Converter

A fixed-slope soft-start method applicable to Buck converters for on-chip integration is proposed to address the issue of varying power stresses (device voltage, current stress) during start-up with different output voltages. The main mechanism involves combining feedback coefficient sampling with a fixed-slope reference voltage to achieve a slow rise in the reference voltage by equating the soft-start charging current to a pulse current through the on-chip integration of a small capacitor. This allows for fixed-slope start-ups for different set output voltages. Spike elimination techniques are employed to address charging current spikes caused by pulse periods, enhancing precise control over the soft-start time. By replacing the traditional resistor divider network with a capacitive divider network in the soft-start method, DC power consumption is minimized. Upon completion of the soft start, a smooth transition to a steady-state operation occurs, with the automatic shutdown of the soft-start module reducing static power consumption. A specific circuit design and layout verification based on 0.18 μm high-voltage BCD technology demonstrates that the proposed method maintains a fixed-slope start-up of approximately 5 mV/μs within the chip’s output range of 0.9 V to 4 V, with a slope control accuracy of up to 98%. The soft-start circuit effectively eliminates surge currents generated during start-up under full load conditions of 3 A and no-load conditions of 0 A, reducing the overall surge current by 44% and enabling a stable voltage rise and the smooth transition to a steady-state operation.

Development of multiple input supply based modified SEPIC DC–DC converter for efficient management of DC microgrid

The development of DC microgrids is reliant on multi-input converters, which offer several advantages, including enhanced DC power generation and consumption efficiency, simplified quality, and stability. This paper describes the development of a multiple input supply based modified SEPIC DC–DC Converter for efficient management of DC microgrid that is powered by two DC sources. Here Multi-Input SEPIC converter offers both versatility in handling output voltage ranges and efficiency in power flow, even under challenging operating conditions like lower duty cycle values. These features contribute to the converter's effectiveness in managing power within a DC microgrid. In this configuration, the DC sources can supply energy to the load together or separately, depending on how the power switches operate. The detailed working states with equivalent circuit diagrams and theoretical waveforms, under steady-state conditions, are shown along with the current direction equations. This paper also demonstrates the typical analysis of large-signal, small-signal, steady-state modeling techniques and detailed design equations. The proposed configuration is validated through the conceptual examination using theoretical and comprehensive MATLAB simulation results. Detailed performance analysis has been done for different cases with various duty ratios. Finally, to show the competitiveness, the multi-input SEPIC topology is compared with similar recent converters.

A novel industrial magnetically enhanced hydrogen production electrolyzer and effect of magnetic field configuration

Hydrogen energy is a clean, zero‑carbon, flexible and abundant secondary energy. The large-scale deployment of industrial hydrogen production equipment is an effective way to improve renewable energy consumption, the efficiency of hydrogen production from water electrolysis is crucial for equipment deployment. In this paper, a novel industrial magnetically enhanced AWE electrolyzer is designed to improve the efficiency of hydrogen production. The structure and assembly method of the magnetic bipolar plate are introduced, the BOP component is designed and an industrial system-level test platform is built. The results show that the magnetic enhanced electrolyzer can effectively improve the hydrogen production efficiency, however, the effects of different magnetic field configurations (Magnetic field horizontal configuration, MFHC; Magnetic field vertical configuration, MFVC; No magnetic field configuration, NMFC) are significantly different. The magnetic field of MFVC are concentrated inside the bipolar plate and perpendicular to the direction of the electric field, and there is almost no magnetic flux leakage inside the cathode and anode cells. The magnetic field and the electric field of the MFHC configuration are not completely perpendicular, the magnetic field distribution is irregular, there are more magnetic flux leakage in the cells, and the magnetic field intensity is obviously greater than that of the MFVC configuration. Compared with NMFC, MFHC and MFVC significantly improved the hydrogen production efficiency, MFHC performance is better, the current density increased by 28.48% (@50 °C-100 L/h-2 V cell voltage-30%wt KOH), DC power consumption was reduced by 6.2% (CC100A-100 L/h-30%wt KOH). The design method and configuration scheme of magnetically enhanced electrolyzer provide a new idea for the industrial application of magnetic fields in AWE hydrogen production equipment.

A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (PDC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S21-3 dB-BW [GHz])/(PDC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature.

Comprehensive study of Class‐‐E/F2 and inverse Class‐‐F power amplifiers for mm‐Wave systems utilizing 130 nm CMOS process

AbstractThis paper presents a comprehensive study of Class‐‐E/F2 and inverse Class‐‐F power amplifiers (PAs) designed for 35–42 GHz millimeter‐wave applications, utilizing a 130 nm CMOS process. The proposed RF PAs are well suited for wide frequency‐band millimeter‐wave and 5G radio transmitters. A comprehensive study of limiting factors in amplifier efficiency is presented in this paper. The study encompasses an analysis of all the factors that restrict the efficiency of the switched power amplifier. The first proposed power amplifier is based on the Class E/F2 architecture, comprising a parallel capacitor, second harmonic resonance circuit, and output matching network. Conversely, the second suggested power amplifier is constructed using the inverse Class‐‐F topology, which includes harmonic termination and matching networks. The harmonic termination circuit incorporates a second harmonic resonance network and utilizes a parasitic capacitor to control the harmonic components. Both the proposed Class E/F2 and inverse Class‐‐F architectures are employed to reshape the drain current and voltage waveforms, aiming to reduce the overlap between them and, consequently, improve efficiency. The suggested power amplifiers comprise a driver Class‐‐AB stage and a power stage constructed based on either the Class E/F2 architecture or inverse Class‐‐F topology, utilizing harmonic termination networks at the output load. Two new designs of high‐Q factor on‐chip finger capacitors have been implemented to improve efficiency and radio frequency performance. Achieving input matching and inter‐stage matching is facilitated by employing two novel on‐chip transformers designed for maximum power transfer. Additionally, an inter‐stage matching inductor is utilized in a cascode configuration to enhance the overall RF performance. The on‐chip transformers, inductors, and finger capacitors are designed using the HFSS software program. S‐parameter files (SNP files) of the designed on‐chip components are extracted and inserted into the simulation tool to ensure accurate results. The proposed Class E/F2 power amplifier achieves a constant power of 14.9 dBm, an extreme power added efficiency (PAE) of 11.7%, and a maximum gain of 13.74 dB. In contrast, the suggested inverse Class‐‐F power amplifier attains a constant power of 15.4 dBm, a peak PAE of 12.6%, and a maximum gain of 14.8 dB. The DC power consumption is 73 and 66 mW for the proposed Class E/F2 and inverse Class‐‐F PAs, respectively, while their active sizes are 0.14 and 0.2 mm2.

Study on Optimization of Deep Purification Process Design of Zinc Oxygen Pressure Acid Leaching Solution

According to the characteristics of high impurity content and complex composition of oxygen pressure leaching (OPL) solution of zinc sulfide concentrate, combined with the quality requirements of large plate electrowinning and automatic plate stripping, the advanced purification process of solution was designed. Through the deep purification process consisting of neutralization indium precipitation and low iron purification, high temperature antimony salt nickel and cobalt removal, copper slag chlorine removal, low temperature zinc powder replacement copper and cadmium removal, fine purification, calcium and magnesium removal, the contents of harmful impurities such as iron, indium, copper, cadmium, nickel, cobalt, fluorine and chlorine in the solution are strictly controlled to ensure that the quality of the deeply purified zinc sulfate solution is qualified and can meet the needs of continuous and stable production. The energy-saving effect of advanced purification process is obvious, and the average DC power consumption per ton of electric zinc is 2880kWh, reaching the advanced level of the same industry in China. The good effect of advanced purification process ensures the successful application of OPL and large plate zinc electrowinning, and improves the technology and equipment level of zinc smelting industry, which has important popularization and application value.

Analysis and Simulation of Current Balancer Circuit for Phase-Gain Correction of Unbalanced Differential Signals

The phase and gain imbalance of a balun output can be adjusted by a differential current balancer (DCB) circuit. The performance of DCB circuit, for correcting the phase (gain) imbalance, is analyzed for a wide range of input signal level, and the accuracy is verified with circuit simulation. To illustrate the phase-error/gain-error (PE/GE) correction, a 30–40[Formula: see text]GHz DCB circuit is designed and simulated in a 180-nm CMOS process. The DCB is examined for input PE, [Formula: see text], of [Formula: see text] and input GE, GA, of [Formula: see text][Formula: see text]dB. Analysis and simulation illustrate an output phase error [Formula: see text] of [Formula: see text] and output gain error [Formula: see text] of [Formula: see text][Formula: see text]dB, over frequency range of 20–50[Formula: see text]GHz. The results of DCB circuit for PE (GE) compensation are compared to that of phase-correction technique (PCT) circuit, illustrating the superior phase (gain) imbalance correction of the DCB circuit with lower NF and DC power consumption.

A wideband and low-power mm-wave variable-gain phase shifter based on a source-switching scheme

This article presents a low-power and wideband variable-gain phase shifter (VGPS) designed and simulated in a CMOS 65 nm technology. It introduces a source-switching scheme for designing a variable gain amplifier (SSVGA) characterized by invariant linearity, impedance, and phase characteristics, showcasing improved gain and bandwidth compared to conventional VGAs. The current-reuse and staggered-tuning techniques are used to reduce power consumption and extend the bandwidth, respectively. The proposed VGPS enables gain tuning without the need for an additional gain tuning block, resulting in reduced chip area and sidelobe levels in phased array radar systems. The proposed VGPS, with a 5-bit resolution, achieves a 3-dB bandwidth of 18 GHz (53.5–71.5 GHz) and exhibits RMS gain error range from 0.23 to 0.5 dB and RMS phase error range from 0.54° to 2.65° with phase calibration based on simulation results. It achieves a peak average gain of 1.2 dB at 58.5 GHz while consuming a DC power consumption of only 5 mW with a 1.2 V power supply voltage. Moreover, it demonstrates a wide gain tuning of 20.6 dB, allowing for flexible gain adjustments.

A Low-power, High-gain and Excellent Noise Figure GaN-on-SiC LNA Monolithic Microwave Integrated Circuit (MMIC) operating at Ka-band for 5G/6G Application

A 25-40 GHz monolithic low-noise amplifier (LNA) is designed and fabricated with the 100 nm gallium nitride on silicon carbide (GaN-on-SiC) technology. This four-stage-cascade monolithic LNA performs a low DC power consumption of 150 mW and noise figure of 1.6-2.2 dB. Moreover, the gain of 34-37 dB with the continuous wave of more than 2 W over 24 hours can be achieved covering the operating bandwidth. Hence, this state-of-art LNA possesses a great potential to be directly integrated with GaN power amplifiers and other microwave components to realize the high-integration, high-reliability, and high-power RF front-end.

Ultra-compact quasi-true time delay for boosting wireless channel capacity.

Massive-data connectivity has driven the need for efficient, directed communications through beamforming arrays1-10. Delay elements are critical in any beamforming signal chain. However, these elements impose fundamental limits on size, channel capacity, power efficiency and effective isotropic radiated power11. Although passive phase shifters do not consume DC power, they suffer from narrow bandwidth, poor phase resolution and low power-handling capacity. They introduce a beam squint, in which different frequency components experience different time delays, blurring signals so that they cannot be resolved. This severely limits the data rate of the wireless link, that is, its channel capacity. Although true time delay (TTD) elements12 solve this problem and service a broad bandwidth, they comprise wavelength-scale transmission lines, making them prohibitively area-inefficient for modern semiconductor processes. Here we address this long-standing problem by introducing a quasi-true time delay (Q-TTD) that miniaturizes TTD elements and breaks fundamental channel-capacity limits of these wireless links. We demonstrate this mechanism for a microwave device implemented in a complementary metal-oxide-semiconductor (CMOS) technology. Key to shrinking the footprint is a reflective-type phase-shifting structure with 3D variable TTD reflectors within a sub-wavelength footprint. This achieves ultra-broadband phase tuning by using them to vary the length of the waveguide's path to ground. They produce a delay-to-area ratio that yields a substantially higher on-chip channel capacity compared with existing state-of-the-art methods. This component, when integrated in arrays, enables high-resolution imaging and low-squint beamforming for wideband communication, on-chip radar and other applications.

N77 Radio Frequency Power Amplifier Module for 5G New-Radio High-Power User Equipment Mobile Handset Applications

This paper presents a highly efficient 5G New-Radio (NR) RF power amplifier module (PAM). The n77 PAM consists of a high-voltage differential-topology 2 μm GaAs HBT power amplifier, a CMOS controller, a silicon-on-insulator (SOI) switch, an integrated passive device (IPD) bandpass filter, a low-noise amplifier (LNA), and a bi-directional coupler. This PAM generates a saturation output power of 32.7 dBm including the loss of the SOI switch and output filter. The designed n77 PAM is tested with a commercial envelope tracker IC (ET-IC). The designed PAM with an ET-IC achieves an ACLR of −37 dBc at a 27 dBm output power with a DFT-s-OFDM QPSK 100 MHz NR signal and saves a dc power consumption of 950 mW compared to the APT mode. For the CP-OFDM 256QAM with the most stringent EVM requirements, it achieves an EVM of 1.22% at 23 dBm and saves 640 mW compared to the APT mode.

A Variable-Gain Low-Noise Amplifier for MedRadio Band Applications

A variable-gain 0.18 μm Complementary Metal- Oxide-Semiconductor (CMOS) Low-Noise Amplifier (LNA) for Medical Device Radiocommunications Service (MedRadio) applications has been designed and verified through simulations in Cadence IC5 with Silterra’s C18G CMOS technology Process Design Kit. Unlike other MedRadio LNAs from previous works, this proposed LNA can vary its gain from just above 10 dB to nearly 30 dB. It consists of three stages; the input-matching stage, the interstage buffer, and the gain-varying stage. The input-matching stage provides an input impedance match and drives the initial gain of the LNA. The inter-stage buffer isolates the input-matching stage from the gain-varying stage. The overall gain of the LNA can be varied and is determined by the variable biasing of the driving transistors of the gainvarying stage. On post-layout simulations with a sourcefollower output buffer, this LNA exhibits a wide-ranging gain from 11.2 dB at 0.49 mW DC power consumption to 29.1 dB at 1.34 mW DC power consumption.

A Fully Integrated Pulling Mitigation Synthesizer for NB-IoT Transmitter

This article presents the pulling mitigation scheme implemented in the frequency synthesizer integrated with the dual-band narrowband-internet-of-things (NB-IoT) transmitter (TX). The proposed pulling mitigation in the synthesizer employs a hybrid phase compensation and sampled filter to mitigate the pulling effects by the transmitter. The synthesizer covers frequencies from 700–900 MHz and 1.7–2 GHz in the low band and high band, respectively, satisfying the dual-band NB-IoT frequency tuning specifications. The proposed pulling mitigation in the synthesizer improves the error vector magnitude (EVM) by 11.5% with 16 quadrature amplitude modulation (QAM) modulation and in single-tone measurements, the achieved pulling suppression is 24 dB. Implemented in 40 nm CMOS, the pulling mitigation occupies a small area of 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.18 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and the dc power consumption is 1 mW with a supply voltage of 1.1 V.

A 27.5–46.2-GHz Broadband Low Noise Amplifier With IP3 Enhancement

This letter presents a 27.5–46.2-GHz broadband low-noise amplifier (LNA) featuring IP3 enhancement. The LNA bandwidth (BW) is extended by implementing dual-resonant input matching and a broadband output network. The LNA IP3 is enhanced by incorporating parallel PMOS and NMOS paths in the second stage, with their output currents combined through a three-winding transformer. Implemented using the GlobalFoundries 45-nm CMOS silicon-on-insulator (SOI) process, the LNA demonstrates 27.5–46.2 GHz effective BW, 2.1 dB minimum noise figure (NF), and 19.8 dB peak gain. The measured IIP3 is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3.6 dBm at 34 GHz under 25.5 mW DC power consumption. Compared to recently reported broadband LNAs with a similar frequency range, this design achieves the state-of-the-art NF, IIP3, and figure-of-merit (FoM).

Gallium arsenide optical phased array photonic integrated circuit.

A 16-channel optical phased array is fabricated on a gallium arsenide photonic integrated circuit platform with a low-complexity process. Tested with a 1064 nm external laser, the array demonstrates 0.92° beamwidth, 15.3° grating-lobe-free steering range, and 12 dB sidelobe level. Based on a reverse biased p-i-n structure, component phase modulators are 3 mm long with DC power consumption of less than 5 µW and greater than 770 MHz electro-optical bandwidth. Separately fabricated 4-mm-long phase modulators based on the same structure demonstrate single-sided Vπ·L modulation efficiency ranging from 0.5 V·cm to 1.22 V·cm when tested at wavelengths from 980 nm to 1360 nm.

60 GHz 7-Bit Passive Vector-Sum Phase Shifter With an X-Type Attenuator

This letter presents the design of a 60 GHz passive vector-sum phase shifter with 7-bit phase resolution. An analog X-type attenuator with complementary voltage control was used for vector modulation. The proposed attenuator is suitable for high-resolution phase shifter design because it is capable of phase inversion and shows a large attenuation range with low-phase variation. The prototype phase shifter fabricated through the 65 nm CMOS process occupies an area of 0.24 mm2 (excluding the bonding pads). The measurement results show that the proposed phase shifter achieves a phase resolution of 2.815∘ while exhibiting an average insertion loss of 14 dB without DC power consumption. The calculated RMS gain and phase error were below 0.55 dB and 0.83-2.36∘, respectively, in the range of 57-67 GHz.

A SiGe HBT D-Band LNA Utilizing Asymmetric Broadside Coupled Lines

This letter presents a D-band low noise amplifier (LNA) implemented in 90 nm SiGe BiCMOS technology and is intended for next-generation communications systems. The LNA is a five-stage staggered common-emitter and cascode design used to simultaneously achieve wide bandwidth and high gain. The LNA utilizes asymmetric broadside coupled lines as interstage impedance transformers to achieve a wideband gain response while constraining power consumption. The presented LNA achieves an in-band gain of 26.5 dB and a bandwidth of 37.6 GHz. The minimum measured NF is 7.2 dB, and the dc power consumption is 20.6 mW. This D-band LNA achieves high gain, wide bandwidth, and low power consumption, resulting in a competitive performance with other D-band LNAs in the literature. The die area of the fabricated LNA is 0.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.86 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> , including pads.