Research on Fixed-Slope On-Chip Soft-Start Method Applied to Buck DC–DC Converter

Abstract

A fixed-slope soft-start method applicable to Buck converters for on-chip integration is proposed to address the issue of varying power stresses (device voltage, current stress) during start-up with different output voltages. The main mechanism involves combining feedback coefficient sampling with a fixed-slope reference voltage to achieve a slow rise in the reference voltage by equating the soft-start charging current to a pulse current through the on-chip integration of a small capacitor. This allows for fixed-slope start-ups for different set output voltages. Spike elimination techniques are employed to address charging current spikes caused by pulse periods, enhancing precise control over the soft-start time. By replacing the traditional resistor divider network with a capacitive divider network in the soft-start method, DC power consumption is minimized. Upon completion of the soft start, a smooth transition to a steady-state operation occurs, with the automatic shutdown of the soft-start module reducing static power consumption. A specific circuit design and layout verification based on 0.18 μm high-voltage BCD technology demonstrates that the proposed method maintains a fixed-slope start-up of approximately 5 mV/μs within the chip’s output range of 0.9 V to 4 V, with a slope control accuracy of up to 98%. The soft-start circuit effectively eliminates surge currents generated during start-up under full load conditions of 3 A and no-load conditions of 0 A, reducing the overall surge current by 44% and enabling a stable voltage rise and the smooth transition to a steady-state operation.