dB SNDR Research Articles

A 0.6-V 86.5-dB DR 40-kHz BW Inverter-Based Continuous-Time Delta–Sigma Modulator With PVT-Robust Body-Biasing

This letter presents a low-power continuous-time delta-sigma modulator (CTDSM) that operates at a 0.6 V supply. The loop filter of the CTDSM is realized with inverter-based integrators and negative-R compensation on each integrator’s virtual ground. A body-biasing technique is used for inverters as well as for negative-Rs to ensure robustness against process, voltage, and temperature (PVT) variations. A prototype CTDSM is fabricated in a 28 nm CMOS process, and achieves 83 dB SNDR, 84 dB SNR, and 86.5 dB DR in a 40-kHz bandwidth, while consuming only 33.6 W from a 0.6 V supply. This corresponds to the state-of-the-art Schreier FoM of 177.3 dB.

A 10-bit SAR ADC using novel LSB-first successive approximation for reduced bitcycles

This paper presents a 10-bit ultra-low power least-significant bit first (LSB-first) successive approximation register analog-to-digital converter used in wearable electrocardiogram monitoring. Compared with the exsiting ones, the number of bitcycles taken in the proposed LSB-first scheme only relates to the difference between two adjacent samples and the capacitor array is reduced by 50%. Fabricated in 65 ​nm CMOS technology within a bio-sensor front-end circuit, the proposed LSB-first SAR ADC occupies an active area of 200 ​× ​450 ​μm2, consumes 60.8 ​nW ​at 10 ​kHz sampling rate, and achieves 58.4 ​dB SNDR.

An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration

This paper presents a wide bandwidth inverter-based continuous time sigma delta (CTSD) analog-to-digital converter (ADC) with a latency-free calibration to suppress the nonlinearity originating from the feedback digital-to-analog converter (DAC). The modulator in the ADC uses a fourth-order architecture with 4-bit quantization. To compensate the excess loop delay (ELD), the proportional-integrating element (PI-element) is employed in the loop filter where the problem of no real solution in conventional PI-element compensation method is solved. In addition, the two-stage inverter-based amplifiers are used in the loop filter to improve power efficiency. To suppress nonlinearity of the 4-bit DAC, a background calibration method based on modified quantizer is proposed which would not introduce additional latency thus ensuring stability of the modulator. The CTSD ADC achieves 64.6 dB SNDR and 71.2 dB SFDR over a 75 MHz signal bandwidth before calibration, and the SNDR and the SFDR can be improved to 67.3 dB and 82.3 dB respectively after calibration. The ADC consumes 38 mW from supply voltages of 1.1/1.8 V with an active area of 0.675 mm2 in 40 nm CMOS.

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC

The power dissipation of a pipelined analog-to-digital converter (ADC) depends on different design strategies. In this brief communication, an 11-bit pipelined ADC consisting of five stages with 2.5 effective bit resolution is described. The circuit combines two main techniques to improve power dissipation, such as sharing OTAs between adjacent ADC stages and dynamic regulation of the OTA biasing according to the stage and subcycle of operation. To reduce the charge injection effect caused by the OTA sharing added circuitry, the ADC uses a topology based on four-input OTAs to reduce the number of transmission gates. The ADC has been fabricated using a standard 0.35- $$\upmu $$ m CMOS process. It consumes 17.85 mW at 10 MSample/s sampling rate. With this resolution and sampling rate, the measurement results show that it achieves 58.20 dB SNDR and 9.38-bit ENOB at 1 MHz input frequency.

Yield constrained automated design algorithm for power optimized pipeline ADC

Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom including the system level down to transistor level parameters, which helps CAD tools to find the optimized solution. It allows designers to choose an optimum scenario considering the trade-off between yield and power consumption. To evaluate the capabilities of this algorithm, a 10-bit pipeline ADC is designed and analyzed. This ADC has 10-bit resolution and 6.3 mW power, 91% yield, 55.3 dB SNDR and 58.8 dB SFDR, which are all in good agreement with the algorithm results. In comparison with similar designs it offers a competitive Figure of Merit (FOM), which proves the capability of this algorithm in finding the optimum solution.

An energy-efficient sample-and-hold circuit in CNTFET technology for high-speed applications

In this paper, a new energy-efficient sample and hold (S/H) circuit based on the proper combination of the Miller-effect and double-sampling technique is presented in the Carbon Nanotube Field Effect Transistor (CNTFET) technology. In order to improve the accuracy and increase the input dynamic voltage range, a new CNTFET-based linearized switch circuit is introduced to be utilized as both the input sampling and output buffer switches. The proposed circuit is simulated in HSPICE using 32 nm CNTFET technology parameters. The simulation results confirm that the proposed S/H circuit properly operates for the data rates of higher than 2 GS/s. In addition, the proposed S/H circuit shows 14-bit resolution, 86.29 dB of SNDR for a 0.4 Vp-p, 218.75 MHz sinusoidal input signal at 2 GS/s sampling rate.

An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS

This brief presents an 8-bit 350-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with 1.5 b/cycle redundancy in 65-nm CMOS. With 12.5% redundancy in conversion cycles, conversion errors caused by capacitor mismatch, offset and DAC settling errors can be addressed. Compared to the conventional 1.5 b/cycle operation, the proposed switching removes the pre-set phase and thus reduces the speed and power penalty. Besides, with this switching scheme, only two reference voltages are needed instead of five in the conventional scheme. The prototype achieves 45.7 dB SNDR at Nyquist input and consumes 2.1 mW from a 1.2 V supply, resulting in a Walden FoM of 38.1 fJ/conversion-step.

Fully Synthesizable Low-Area Analogue-to-Digital Converters With Minimal Design Effort Based on the Dyadic Digital Pulse Modulation

In this paper, fully-synthesizable Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) suitable for low-cost integrated systems are proposed both for voltage and current input. The proposed ADCs are digital in nature and are based on the Dyadic Digital Pulse Modulation (DDPM) Digital-to-Analog (DAC), instead of a traditional capacitive DAC. The proposed fully-digital ADC architectures enable low-effort design, silicon area reduction, and voltage scaling down to the near-threshold region. Compared to traditional analog-intensive designs, their digital nature allows easy technology and design porting, digital-like area shrinking across CMOS technology generations, and also drastically reduced system integration effort through immersed-in-logic ADC design. The voltage-input ADC architecture is demonstrated with a 40-nm testchip showing 3,000-μm 2 area, 6.4-bit ENOB, 2.8kS/s sampling rate, 40.4dB SNDR, 49.7dB SFDR, and 3.1μW power at 1V. A current-input ADC is also demonstrated for direct current readout without requiring a trans-resistance stage. 40-nm testchip measurements show a 5-nA to 1-μA input range, 4,970μm 2 area, 6.7-bit ENOB and 2.2-kS/s sample rate, at 0.94-μW power. Compared to the state of the art, the proposed ADC architecture exhibits the highest level of design automation (standard cell), lowest area, and the unique ability to cover direct acquisition of both voltage and current inputs, suppressing the need for transresistance amplifier in current readout.

A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications

This article presents a 16-channel 5 GS/s time-interleaved (TI) SAR ADC for a direct-sampling receiver that employs a digital-mixing background timing mismatch calibration to compensate for timing-skew errors. It uses a first-order approximation to obtain the derivative of the autocorrelation of the input signal, subsequently used to evaluate the explicit amount of the timing-skew. Therefore, this allows a digital background calibration of the timing-skew, avoiding extra analog circuits. The proposed 16-channel TI ADC uses a splitting-combined monotonic DAC switching method for the individual SAR channel to achieve a trade-off of simple switching and small common-mode voltage variation of the comparator. The prototype, implemented in 28 nm CMOS, reaches a 48.5/47.8 dB SNDR with an input signal of 2.38/4.0 GHz after the proposed background timing mismatch calibration, respectively. Furthermore, the ADC core’s power consumption is 29 mW sampling at 5 GS/s, with a Walden FoM of 26.7 fJ/conv.-step and a Schreier FoM of 157.9 dB.

Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications

In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching (DEM) logic can be applied even for high-speed implementation, which helps to decrease power dissipation. Two prototypes using slightly different input branch topologies were fabricated with a 0.18 um 2-poly and 4-metal CMOS process, and measured to demonstrate the effectiveness of the proposed circuit technique. The sampling capacitor and feedback DAC capacitors were separated in prototype A, while they were shared in prototype B. The prototypes achieved 81.2 dB and 72.4 dB of SNDR in a 2.1 MHz signal band, respectively.

A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA

This brief presents the design and implementation of a new blocker tolerant wideband continuous-time delta-sigma modulator. Using a customized digital integrator with inherent data-weighted averaging at the back-end of the modulator, the power consumption of the quantizer is reduced while the speed of operation is increased. Additionally, by using a single amplifier biquad structure in the loop filter, the number of op-amps is reduced, thus reducing the analog power consumption. Also, the modulator robustness to the out-of-band blocker is improved by increasing the number of levels in the digital integrator and feedback DACs. The out-of-band blocker tolerance is improved by 3 dB compared to a conventional CIFF-B delta-sigma modulator with a minimal increase in the power consumption. The proposed architecture has been implemented in a 65-nm CMOS technology and operates at a 250 MHz sampling frequency. It achieves 73.5 dB SNR, 72.4 dB SNDR, and 92 dB SFDR over a 7-MHz bandwidth and a Walden figure-of-merit of 341 fJ/conversion.

A 12-bit 350 MS/s Single-Channel Pipeline ADC with 75 dB SFDR in 0.18 μm BiCMOS

A 12-bit 350[Formula: see text]MS/s ADC with 75[Formula: see text]dB SFDR fabricated in 0.18[Formula: see text][Formula: see text]m SiGe BiCMOS process is presented. To improve the power efficiency, the ADC employs a novel residue amplifier (RA) by exploiting the hetero-junction bipolar transistor (HBT). We also propose a fast comparator to save time for the residue settling of pipeline stages. A fully integrated reference buffer with “negative bootstrap power” (NBP) is proposed to improve both high power supply rejection ratio (PSRR) and ground supply rejection ratio (GSRR). A bandgap reference (BGR) with ultra-low leakage current start-up loop is also presented. The measured results show that with Nyquist input, the SFDR achieves 75[Formula: see text]dB and 63[Formula: see text]dB SNDR up to 350[Formula: see text]MS/s and consumes 180[Formula: see text]mW (only ADC core) with 580[Formula: see text]fj/cov Waldon FOM.

2+2 MASH incremental ADC

In this paper, 2+2 multi-stage noise shaping incremental ΔΣ ADC for wideband and high accuracy application is described and analyzed. The modulator introduced inter-stage gain to reduce the quantization noise without adding any hardware. Also, a gain scaling technique was used to decrease the power consumption by reducing the integrators’ output swing. A proof-of-concept prototype was fabricated with 0.18 μm 2P4M CMOS process. It achieved a 94.2 dB dynamic range and 74.8 dB SNDR in the 1.25 MHz signal band. The total power consumption is 67.1 mW with dual power supplies (analog 3.3 V, digital 1.8 V).

A CT ΔΣ modulator using 4-bit asynchronous SAR quantizer and MPDWA DEM

The current paper aims at presenting a low-power second-order input-feedforward continuous-time (CT) ΔΣ modulator for audio applications. It uses a 4-bit asynchronous successive approximation register (SAR) quantizer which is more power efficient than the usual flash converter. Furthermore, in order for the proposed modulator to reduce the noise stemming from the component mismatches of the feedback digital-to-analog converter (DAC), it applies a modified partitioned data weighted averaging (MPDWA) dynamic element matching (DEM) so as to solve the DWA DEM-in band-tone problem. Despite the implementation of MPDWA, no further delay caused in the ΔΣ feedback loop compared to the conventional DWA. The implementation of the above-mentioned DEM in the modulator and required reforms have led to a new design with better performance and favorable figure of merit (FOM) value. The designed modulator which is simulated using 0.18 µm CMOS technology, achieves 84.17 dB SNDR for 20 kHz signal bandwidth and dissipates 54 µW while its FOM is obtained about 143 fJ/conv.-step.

An Oversampling Stochastic ADC Using VCO-Based Quantizers

An oversampling stochastic analog-to-digital converter is presented. This stochastic converter spatially averages quantization errors in multiple voltage-controlled oscillator (VCO)-based quantizers. Unlike other stochastic converters, this proposed architecture does not require an inverse Gaussian cumulative density function estimator. The digital adder becomes an ideal estimator due to uncorrelated quantization errors, which can be modeled as a uniformly distributed random variable. Because of the simple open-loop structure, this stochastic converter can easily be synthesized and reconfigured. The proof-of-concept prototype is implemented in a 0.18 $\mu \text{m}$ CMOS process. The prototype employs eight VCO-based quantizers and validates the extra 9 dB signal to quantization noise ratio improvement from quantization error spatial averaging. The measurements further demonstrate 54.2 dB and 45.4 dB SNDR for 50 MHz and 100 MHz bandwidths, while dissipating 116 mW of power.

A Fully Integrated Analog Front End for Biopotential Signal Sensing

A low-power fully-integrated analog front end for biopotential sensors is proposed. The signal conditioning circuitry features an integrating sampler and a digital-assisted electrode offset-cancellation loop. The chip is fabricated in a standard 0.18- $\mu \text{m}$ CMOS process. The supply voltage is 1.2 V and the quiescent current is $7.7~\mu \text{A}$ . Measurement results show that the analog front end achieves an in-band gain of 58 dB, a noise spectrum density of 46nV/ $\sqrt {\text{Hz}} $ and can tolerate ±60 mV electrode offset. The THD is below 1% with a 2mVpp input. The analog signal is converted to digital code at 5kS/s by a 12-bit SAR ADC with 63.2 dB SNDR. The prototype IC is experimented with capturing ECG on human beings.

A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS

This brief presents a high-speed successive approximation register analog-to-digital converter (ADC) with nonbinary searching technique. By inserting redundancy in the first five decision steps, the digital-to-analog converter (DAC) settling errors can be tolerated and settling time can thus be reduced. In addition, split capacitor technology has also been adopted to further boost the conversion speed. With split switching method, no common mode voltage is needed in DAC reset phase and dynamic offset can be removed as well. Full adder-based encoder is employed to convert the raw 11-bit to 10-bit binary codes, showing less power penalty. The prototype ADC fabricated in 65-nm CMOS achieves 51.1 dB SNDR and 62.3 dB SFDR at 150-MS/s sampling rate. It consumes 1.4 mW, resulting in a Walden figure of merit of 31.8 fJ/conversion step.

A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-μm CMOS

A 10-bit 100 MS/s energy-efficient successive-approximation analog-to-digital converter (SAR ADC) is presented in this paper. In order to improve the conversion rate and reduce power consumption as well, a modified spilt-capacitor VCM-based switching scheme is proposed. By utilizing the LSB capacitors to obtain the last-bit, the proposed switching scheme could decrease the area of capacitive DAC. Moreover, by modifying the switching behaviors of the most significant bit (MSB) and 2nd-MSB, the conversion rate could be improved. The prototype SAR ADC fabricated in 0.18 μm CMOS achieves 53.68 dB SNDR and 62.85 dB SFDR at 100 MS/s sampling rate. The active area of the core is 0.216 mm2. It consumes 5.23 mW with 1.8 V supply, resulting in a Walden figure of merit (FoM) of 123.2 fJ/conversion step.

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver * * Project supported by the National Natural Science Foundation of China (Nos. 61471245, U1201256), the Guangdong Province Foundation (No. 2014B090901031), and the Shenzhen Foundation (Nos. JCYJ20160308095019383, JSGG20150529160945187).

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator. A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator. The proposed modulator uses sampling capacitor sharing switched capacitor integrator, and achieves a very small feedback coefficient by a series capacitor network, and those two techniques can dramatically reduce capacitor area. Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation. This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and -1 MHz IF with 48 MHz clock. The chip is fabricated with SMIC 0.18 μm CMOS technology, it achieves a total power current of 2.1 mA, and the chip area is 0.48 mm2.

A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS

A 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) was implemented in a 14 nm SOI FinFET CMOS technology, achieving 59.59 dB SNDR at 50 MS/s while consuming 41.3 µW power. Several techniques were used to increase the energy efficiency while ensuring the linearity. First, a segmented architecture with a 5-bit coarse ADC and an 11-bit fine ADC was used. The aligned Switching with Skip (ASS) method was used to generate the five MSBs of the fine ADC from the computed coarse ADC bits, saving 58% switching power compared with non-segmented architecture with merged capacitor switching (MCS) method. Second, VCM-based MCS scheme is used for SAR bit resolving, saving 85.72% switching power compared with traditional SAR switching. Third, the dual supply mode with analog at 0.8 V and digital at 0.4 V was used. This reduces the total digital logic power consumption by 23% comparing with that using the single supply at 0.8 V. The differential architecture was used to minimize the common mode non-idealities. The proposed ADC has been implemented in a 14 nm SOI FinFET technology and achieved a peak Figure of Merit (FoM) of 1.07 fJ/Conversion-step with simulation results.