An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS

Abstract

This brief presents an 8-bit 350-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with 1.5 b/cycle redundancy in 65-nm CMOS. With 12.5% redundancy in conversion cycles, conversion errors caused by capacitor mismatch, offset and DAC settling errors can be addressed. Compared to the conventional 1.5 b/cycle operation, the proposed switching removes the pre-set phase and thus reduces the speed and power penalty. Besides, with this switching scheme, only two reference voltages are needed instead of five in the conventional scheme. The prototype achieves 45.7 dB SNDR at Nyquist input and consumes 2.1 mW from a 1.2 V supply, resulting in a Walden FoM of 38.1 fJ/conversion-step.