An energy-efficient switching scheme with low common-mode voltage variation and no-capacitor-splitting DAC for SAR ADC

Abstract

An energy-efficient switching scheme with low common-mode voltage variation and simple capacitor array for successive approximation register (SAR) analog-to-digital converters (ADCs) is presented. The proposed scheme adopts simple binary weighted capacitor array without capacitor-splitting, and consumes no switching energy in the first two comparison cycles. The behavioural simulation shows the proposed scheme achieves 98.45% saving in switching energy and 75% saving in total capacitors area compared with the conventional switching scheme. Furthermore, the voltage variation on positive and negative sides of capacitive digital-to-analog converter (CDAC) is equal in magnitude and opposite in direction until the last bit cycle, therefore the dynamic common-mode voltage variation range of CDAC is only 0.5LSB. Employing the proposed switching scheme, a 10-bit 200-kS/s 0.6-V SAR ADC is designed in 40-nm CMOS technology. Post-layout simulation results indicate that a SNDR of 57.1 dB can be achieved with the Nyquist input at 200-kS/s. The figure-of-merit of the proposed ADC is 1.37fJ/conversion-step.