Algorithm and implementation of digital calibration of fast converging Radix-3 SAR ADC

Abstract

This paper presents a calibration technique for radix-3 successive approximation register (SAR) analog-to-digital converter (ADC) that was proposed in [1]. The main advantage of radix-3 SAR ADC is it generates 1.6 bits per conversion cycle which is 60% faster than the conventional radix-2 SAR. However the performance largely depends on matching of capacitors in digital to analog converter (DAC). Effect of capacitor mismatches on signal-to-quantization-noise ratio (SQNR) is demonstrated and calibration technique is simulated in 180nm CMOS technology. This calibration technique does not require any extra capacitor DAC and is programmable for any radix-3 SAR ADC. 7 bit Radix-3 ADC is designed which can achieve signal to noise and distortion ratio (SNDR) of 67 dB up to 10% capacitor mismatch.