An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration

Abstract

This paper presents a wide bandwidth inverter-based continuous time sigma delta (CTSD) analog-to-digital converter (ADC) with a latency-free calibration to suppress the nonlinearity originating from the feedback digital-to-analog converter (DAC). The modulator in the ADC uses a fourth-order architecture with 4-bit quantization. To compensate the excess loop delay (ELD), the proportional-integrating element (PI-element) is employed in the loop filter where the problem of no real solution in conventional PI-element compensation method is solved. In addition, the two-stage inverter-based amplifiers are used in the loop filter to improve power efficiency. To suppress nonlinearity of the 4-bit DAC, a background calibration method based on modified quantizer is proposed which would not introduce additional latency thus ensuring stability of the modulator. The CTSD ADC achieves 64.6 dB SNDR and 71.2 dB SFDR over a 75 MHz signal bandwidth before calibration, and the SNDR and the SFDR can be improved to 67.3 dB and 82.3 dB respectively after calibration. The ADC consumes 38 mW from supply voltages of 1.1/1.8 V with an active area of 0.675 mm2 in 40 nm CMOS.