Abstract

A continuous-time (CT) sigma-delta ($\Sigma\Delta$) modulator employing nonreturn-to-zero (NRZ) digital-to-analog converter (DAC) and pulse shaping to achieve the performance of reducing the impact of clock jitter is presented and implemented in tsmc 0.18 um CMOS technology. The proposed $\Sigma\Delta$ modulator with RF receiver comprises a third-order RC operational-amplifier-based loop filter, a 4-bit internal quantizer operating at 160 MHz, three DACs operating at 1.2 V supply voltage and2.4GHz receiver for wireless respiratory detection. The NRZ DAC with quantizer excess loop delay compensation is set to be half the sampling period of the quantizer. The proposed design incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. Measured results proposes that the $\Sigma\Delta$ modulator achieves SNDR of 56.5 dB and ENOB of 9.1-bit over a 10 MHz band at an over-sampling ratio (OSR) of 8. The proposed receiver antenna proposed return loss is lower than 2. The proposed modulator dissipates 10.1 mW and including pads, the chip area is $0.363mm^{2}$.

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