Abstract
In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching (DEM) logic can be applied even for high-speed implementation, which helps to decrease power dissipation. Two prototypes using slightly different input branch topologies were fabricated with a 0.18 um 2-poly and 4-metal CMOS process, and measured to demonstrate the effectiveness of the proposed circuit technique. The sampling capacitor and feedback DAC capacitors were separated in prototype A, while they were shared in prototype B. The prototypes achieved 81.2 dB and 72.4 dB of SNDR in a 2.1 MHz signal band, respectively.
Highlights
At present, there is an increasing need for low-power analog-to-digital converters (ADCs) due to the demands of the portable market and the desire for longer battery life [1]
Medium accuracy and wideband operations are required for digital video and xDSL modems with the continuing advancement of CMOS technology
In prototype A, the sampling capacitor was separated from DAC capacitors, while they were shared in prototype B
Summary
There is an increasing need for low-power analog-to-digital converters (ADCs) due to the demands of the portable market and the desire for longer battery life [1]. The architecture has significant advantages, it requires a fast comparator and DEM logic which dissipates more power, because only non-overlapping time between φ1 and φ2 is available to operate the comparator and dynamic element matching (DEM) to filter out the DAC mismatch. The propagation propagation delay delay of of the the barrel barrel trade-off shifter is constant and independent of the shifter value or size because input data transfers to the shifter is is constant constant and and independent independent of of the the shifter shifter value value or or size size because because input input data data transfers transfers to to the the shifter output passing through only one gate
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