Current Mirror Circuit Research Articles

Low Power High Speed Differential CurrentComparator

A low power high speed differential current comparator having weak current operation has been presented in this paper. The comparator proposed is a three stage process. It utilizes a modified Wilson's current mirror circuit for current to voltage conversion for its first stage followed by differential amplifier stage and buffer stage. The current comparator is simulated using Cadence Virtuoso 0.18μm CMOS technology and it can successfully generate valid output response for a range of input frequencies. Working at a supply of 1.8V, the comparator is capable of sensing a minimum difference of 22nA for 4μA reference current. In addition power dissipation of this circuit is as low as 226μW and shows a swift response resulting in a propagation delay which is less than 0.8ns for an input difference of 1μA.

Neuron Circuit Using a Thyristor and Inter-neuron Connection with Synaptic Devices

We propose a simple and compact thyristor-based neuron circuit. The thyristor exhibits bi-stable characteristics that can mimic the action potential of the biological neuron, when it is switched between its OFF-state and ON-state with the help of assist circuit. In addition, a method of inter-neuron connection with synaptic devices is proposed, using double current mirror circuit. The circuit utilizes both short-term and long-term plasticity of the synaptic devices by flowing current through them and transferring it to the post-synaptic neuron. The double current mirror circuit is capable of shielding the pre-synaptic neuron from the post synapticneuron while transferring the signal through it, maintaining the synaptic conductance unaffected by the change in the input voltage of the post-synaptic neuron.

A novel CMOS-MEMS integrated pressure sensing structure based on current mirror sensing technique

Purpose– The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors.Design/methodology/approach– This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge.Findings– The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits.Originality/value– The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.

Comparison of Current Mirrors Designed with TFET or FinFET Devices for Different Dimensions and Temperatures

The continuous MOSFET device scaling turned short channel effects and leakage currents into major issues, in a way that new technologies should be considered for further technology nodes. In this context, Tunnel Field Effect transistors (TFETs) are a promising alternative, in which gate controlled band-to-band tunneling (BTBT) replaces drift-diffusion in providing carrier injection[1-2]. The built-in tunnel barrier makes it possible to reach subthreshold swing (SS) values lower than ln(10).k.T/q (60mV/dec at room temperature), reducing power dissipation and leakage currents[1-2]. However low on-state current and ambipolarity are relevant issues, some simple circuits can be used to infer how recent devices compare to traditional structures. In this work, TFET devices have been studied based on experiments and simulations of a basic current mirror. Their performance has been compared to FinFETs for temperatures ranging from 300K to 500K. Fig.1 represents schematically the basic current mirror, with a fixed bias in the input transistor and a varying drain voltage applied to the output device. All measurements and simulations have been performed with VS1=VS2=1.7V and with VDS2ranging from -0.5V to 1.0V. Input and output drain currents have been analyzed. First of all, this circuit has been experimentally studied, making use of TFETs (Fig.2) and FinFETs (Fig.3) with different values of channel length (1µm and 10µm) and width (1µm and 0.25µm). Since for TFET the input transistor is under a fixed bias, its drain current is basically constant. Meanwhile, the output drain current decreases when VD2gets closer to 1.0V, since it is not in the “saturation-like” region anymore. Comparing Figures 2 and 3, it is clear that TFETs and FinFETs, respectively, present the same susceptibility to the channel width variation. On the other hand, it is quite interesting to notice the difference in terms of channel length dependence. Comparing IDSwhen L gets 10 times larger, FinFETs present the expected 10 times decrease, while TFETs reveal a reduction of no more than 20%, since TFET is not as length dependent as FinFET. Based on these observations, simulations have been performed to reveal the channel length influence on the suitability of both TFETs and FinFETs for current mirror circuits. All the simulations have been performed for an input transistor with L1 = 60nm, while the output transistor had L2 ranging from 20nm to 100nm. Figure 4 shows the IDS2/IDS1 ratio for each case when VDS2=0V, with the perfect matching situation represented by L2=L1=60nm. The results show that TFET is much less dependent on L2 than FinFET. Therefore, it is interesting to notice that the circuit presents a very good mirror behavior even when the transistors channel lengths do not exactly match. This is a consequence of the previously mentioned TFET working principle, with the tunneling happening quite close to the source/channel junction. The drain current is affected by L2only when it gets lower than 40nm, which may be explained by the impact of DIBT (drain induced barrier thinning) on TFETs[3]. On the other hand, a circuit with FinFETs loses its ability to mirror the input current when L2 changes. For instance, when L2 changes from 40nm to 100nm, the output drain current variation reaches 50%, while it varies less than 10% for TFETs. In the worst-case scenario for both of them (L2=20nm), the output drain current deviation from the perfect matching situation reaches 80% for TFETs and 230% for FinFETs. Finally, Fig.5 illustrates the temperature impact on the current mirror output current, revealing 2 main differences between TFETs and FinFETs. The first one is the opposite trend, with an ascending curve only for the TFET case. This may be explained by the differences in the transport mechanisms for each case. In TFET devices, higher temperatures increase band-to-band tunneling, which is the most important component for high values of VDS. Meanwhile, the mobility in FinFETs is degraded, resulting in a drain current decrease to almost half of its original value. Besides, dashed lines in Fig.5 reveal the susceptibility to the output drain voltage. These curves show the obtained results for VD2=-0.5V and VD2=+0.5V. While for TFETs this variation causes an output current deviation of 6%, for FinFETs the deviation reaches almost 30%. In other words, circuits with TFETs tend to present a larger compliance voltage, which is exactly the maximum voltage variation that still results in an acceptable output current. Therefore, TFETs present a better suitability in terms of mirroring the input current even for output bias variations. [1] W.M.Reddick et al.,Appl.Phys.Lett.,67,494-496,(1995). [2] T.Krishnamohan et al.,Tech.Dig. IEDM 2008,947-950,(2008). [3] M.D.V.Martino et al.,SBMicro 2014,1,1-4,(2014). Figure 1

A 1.2-V 4.2-<formula formulatype="inline"> <tex Notation="TeX">$\hbox{ppm}/^{\circ}\hbox{C}$</tex></formula> High-Order Curvature-Compensated CMOS Bandgap Reference

This study presents a high-precision CMOS bandgap reference (BGR) circuit with low supply voltage. The proposed BGR circuit consists of two BGR cores and a curvature correction circuit, which includes a current mirror and a summing circuit. Two BGR cores adopt conventional structures with the curvature-down characteristics. A current-mirror circuit is proposed to implement one of the BGR cores to have the curvature-up characteristic. Selection of the appropriate resistances in the BGR cores results in one reference voltage with a well balanced curvature-down characteristic and another reference voltage with an evenly balanced curvature-up characteristic. The summation of these reference voltages is proposed to achieve a high-order curvature compensation. This curvature correction circuit causes the proposed BGR circuit without any trimming to show a measured temperature coefficient (TC) as low as 4.2 ppm/°C over a wide temperature range of 160 °C (-40 ~ 120 °C) at a power supply voltage of 1.2 V. The average TC for 8 random samples is approximately 9.3 ppm/°C. The measured power-supply rejection ratio (PSRR) of -30 dB is achieved at the frequency of 100 kHz. The total chip size is 0.063 mm 2 with a standard 0.13-μm CMOS process.

Non-uniformity study on readout circuit for uncooled IR detector

For long line uncooled infrared detectors, the non-uniformity of different detecting elements is the key parameter in measuring the circuit performance. So far there have been few research reports in this area. Most uncooled infrared detector circuits require corresponding blind detector for readout circuit design, which increases the complexity of uncooled infrared detector. In addition, the performances of these circuits need to be further improved in practical applications. In order to achieve high performance readout of the long line uncooled infrared detectors, a kind of 160 element readout circuit based on current mirror is designed in this paper. The readout circuit is composed of current mirror input part, capacitor feedback transimpedance amplifier (CTIA), and correlated double sampling (CDS) output circuit. The circuit is fabricated by using the 0.5 micron technology. The non-uniformity of circuit is obviously improved by reasonable parameter setting and current mirror circuit layout. Transconductance amplifier CTIA with capacitance negative feedback is used in the circuit. The integral capacitor consists of three capacitors whose capacitances are 10 pF, 20 pF and 20 pF respectively, thus the circuit can realize different integration capacitances, which forms different magnifications. The circuit can meet different response rates of uncooled detectors. Folded-cascode structure is adopted as the CMOS differential amplifier. The open loop gain is over 80 dB. This single-state folded-cascode construct can overcome the two-stage amplifier’s disadvantages, which easily leads to oscillations. The CDS N SF (source follow) and P SF are adopted as the circuit output, the output swing can easily be greater than 2 V. On average, the CDS N SF and P SF power consumptions are very low. So the total power consumption of 160 line circuit is lower than 100 mW. In the test, the non-uniformity of the readout circuit decreases from 10% to 1%. This result is in accordance with simulation result on non-uniformity. The other test results of total power consumption and the output amplitude also agree with simulation results. The readout circuit has good noise characteristics and the output noise is lower than 1 mV. When the readout circuit and uncooled infrared detector are connected, the infrared signal can be well read out. When the integration time is 20 μups, the device response is 0.294 mV/Ω. The overall system performance is very good. This circuit design based on current mirror has laid the technical foundation for developing readout circuit of the very large scale uncooled infrared detector in the future.

An Investigation of Single-Event Transients in C-SiGe HBT on SOI Current Mirror Circuits

The single-event effect sensitivity of three different commonly employed current mirror circuits, as well as an unconventional inverse-mode current mirror, all implemented in C-SiGe (NPN + PNP) HBT on SOI technology are investigated. Comparisons of the measured data of the basic NPN and PNP current mirror circuits show higher single-event radiation tolerance of PNP SiGe HBTs compared with NPN SiGe HBTs. The concept of utilizing inverse-mode SiGe HBTs in current mirror circuits is investigated. Measurement results validate the feasibility of employing inverse-mode PNP SiGe HBTs in current mirrors and show an excellent resilience against ion-strikes. Full 3-D NanoTCAD models of the SiGe HBTs are developed and used in mixed-mode TCAD simulations (within Cadence) to validate the measurement results. Finally, based on the measurement data and analysis of the four current mirrors, some practical suggestions and observations are offered for operation of such circuits in extreme environments.

Self-Configurable Current-Mirror Circuit With Short-Circuit and Open-Circuit Fault Tolerance for Balancing Parallel Light-Emitting Diode (LED) String Currents

Current imbalance among parallel light-emitting diode (LED) strings could put excessive current and thermal stress on some of the LEDs in the systems, resulting in reduction in system lifetime. For LED road lighting systems, reliability is the paramount factor. This paper first explains how existing current-mirror (CM) circuits cannot cope with LED open-circuit faults and then describes a self-configurable CM circuit that can withstand open-circuit faults in LED systems with parallel LED strings. The ability to withstand open-circuit faults means that the LED systems can still function with reduced luminous output even if one LED string is cut off. The proposed circuit, which retains the feature of not requiring an auxiliary dc power supply, has been practically implemented and successfully tested in a 70-W LED system with three parallel strings.

Characterization of Thermally Induced Stress in IC Packages Using PiFETs Over a Temperature Range of −180°C to 80°C

In certain applications, IC packages may be exposed to extreme temperatures and knowledge of thermally induced stress aids the prediction of performance degradation or failure of the IC. In the devices that are used in extreme conditions, the stress is caused mainly by the mismatch in expansion of various materials triggered by the different coefficients of thermal expansion. This work performed in this study is conducted using NMOS current mirror circuits that are cycled through a wide temperature range of −180°C to 80°C. These circuits are highly sensitive to stress and provide well-localized measurements of shear stress. The sensors are fabricated in such a way that the effects of certain stress components are isolated. These sensors are also temperature compensated so that only the effect of mechanical stress components is observed and changes in device performance due to temperature changes are minimal. Current readings obtained from the sensors are used to extract the shear stress component. Finite element simulations, using expected materials performance parameter information were also performed for similar packages and these results are compared to the measured results.

Organic Digital Logic and Analog Circuits Fabricated in a Roll-to-Roll Compatible Vacuum-Evaporation Process

We report the fabrication of a range of organic circuits produced by a high-yielding, vacuum-based process compatible with roll-to-roll production. The circuits include inverters, NAND and NOR logic gates, a simple memory element (set-reset latch), and a modified Wilson current mirror circuit. The measured circuit responses are presented together with simulated responses based on a previously reported transistor model of organic transistors produced using our fabrication process. Circuit simulations replicated all the key features of the experimentally observed circuit performance. The logic gates were capable of operating at frequencies in excess of 1 kHz while the current mirror circuit produced currents up to 18 μA.

Low power high output impedance high bandwidth QFGMOS current mirror

Current mirror is a basic block of any mixed-signal circuit for example in an analog-to-digital converter. Its precise performance is the key requirement for analog circuits where offset is a measure issue. The key parameter which defines the performance of current mirror is its input/output impedance, input swing, and bandwidth. In this paper, a low power design of current mirror using quasi-floating gate MOS transistor is presented. The proposed current mirror boosts its output impedance in range of giga-ohm through use of regulated cascode structure followed by super-cascode. Another improvement is done in reduced input compliance voltage limits with the help of level shifter. The proposed current mirror operates well for input current range 0–700μA with an input and output impedance of 160Ω and 8.55GΩ respectively and high bandwidth of 4.05GHz. The total power consumption of the proposed current mirror is about 0.84mW. The low power consumption with enhanced output impedance and bandwidth suits proposed current mirror for various high-speed analog designs. Performance of the presented current mirror circuit is verified using HSpice simulations on 0.18μm mixed-mode twill-well technology at a supply voltage of ±0.5V.

All Current-Mode Operate in High Precision Vector Summation Circuit

This paper presents all current-mode operate in high precision vector summation circuit used CMOS technology 0.5 um level 3. The structure of the circuit consists of two parts: a squared and current mirror circuit. This is designed to work in all current modes which relies equations, quadratic functions. Make use fewer transistors, makes it easy to understand, but the number of transistors with high fidelity and distortion of the signal. The simulation of the circuit relies on the CMOS during saturation. With input sinusoidal input signal displayed by using the PSpice circuit analysis.

CMOS self-powered monolithic light-direction sensor with digitalized output.

We present a novel self-powered chip to detect the direction of incident light. This chip directly provides digitized output without the need of any off-chip power supply or optical or mechanical components. The chip was implemented in a standard 0.5 μm CMOS process. A microscale metal baffle was created by stacking all metal layers, contacts, and vias available in the process to produce on-chip shadowing. N-well/p+ photodiode arrays are located on both sides of the baffle to sense light. The photocurrent generated by a photodiode depends on the size of the photodiode and the shadowing. The shadowed area depends on the incident angle of the light. A current mirror circuit is used to compare the currents generated by the photodiodes on the opposite sides of the baffle and, consequently, provide a digital signal to indicate the incident light angle. Compared with the ideal linear digital light-angle detector with the same resolution, the presented sensor achieved the maximum error of only 2 deg over 110 deg test range.

A New Transmission Gate Cascode Current Mirror Charge Pump for Fast Locking Low Noise PLL

Charge Pump in a phase locked loop (PLL) generates non-ideal effects such as current mismatches at the output node and switching errors at the pull up and pull down networks. This work presents a novel transmission gate cascode current mirror charge pump circuit. The switches incorporated in this work are Transmission Gates which help to reduce various switching errors, and only one supply independent reference current source is used to have a minimum current mismatch. The performance analysis carried out in the Cadence design environment, and it is observed that the loop locks in 25 ns which is 50 % faster than the conventional charge pump. The control voltage absolutely has no ripple in it after locking which reduces the reference spur further. It could be achieved because the current mismatch is only about 7 %. This PLL operates at 2.5 GHz having a wide lock range of 0.5---2.8 GHz where average power consumption is 1.74 mW. Due to the use of cascade current mirror circuits, the output voltage swing that can be obtained is 1.79 V.

Advanced Circuit-Level Model of Magnetic Tunnel Junction-based Spin-Torque Oscillator with Perpendicular Anisotropy Field

Interest in spin-torque oscillators (STOs) has been increasing due to their potential use in communication devices. In particular the magnetic tunnel junction-based STO (MTJ-STO) with high perpendicular anisotropy is gaining attention since it can generate high output power. In this paper, a circuit-level model for an in-plane magnetized MTJSTO with partial perpendicular anisotropy is proposed. The model includes the perpendicular torque and the shift field for more accurate modeling. The bias voltage dependence of perpendicular torque is represented as quadratic. The model is written in Verilog-A, and simulated using HSPICE simulator with a current-mirror circuit and a multi-stage wideband amplifier. The simulation results show the proposed model can accurately replicate the experimental data such that the power increases and the frequency decreases as the value of the perpendicular anisotropy gets close to the value of the demagnetizing field.

Circuit-Level Model of Phase-Locked Spin-Torque Oscillators

Spin-torque oscillators (STOs) are new oscillating devices based on spintronics technology with many advantageous features, i.e., nanoscale size, high tunability, and compatibility with standard silicon processing. Recent research has shown that two electrically connected STOs may operate as a single device when specific conditions are met. To overcome the limitation of the small output power of STOs, the phase-locking behavior of multiple STOs is hereby extensively investigated. In this paper, we present a circuit-level model of two coupled STOs considering the interaction between them such that it can represent the phase-locking behavior of multiple STOs. In our model, the characteristics of each STO are defined first as functions of applied DC current and external magnetic field. Then, the phase-locking condition is examined to determine the properties of the two coupled STOs on the basis of a theoretical model. The analytic model of two coupled STOs is written in Verilog-A hardware description language. The behavior of the proposed model is verified by circuit-level simulation using HSPICE with CMOS circuits including a current-mirror circuit and differential amplifiers. Simulation results with various CMOS circuits have confirmed the effectiveness of our model.

Applicability of Redundant Pairs of SOI Transistors for Analog Circuits and Their Applications to Phase-Locked Loop Circuits

Redundant pairs of SOI transistors have been utilized as a Radiation Hardening-By-Design technique. Their applicability was subsequently extended for analog circuits, such as current mirror circuits, and successfully demonstrated with a phase-locked loop circuit.

CMOS-MEMS Based Current Mirror MOSFET Embedded Pressure Sensor for Healthcare and Biomedical Applications

This paper reports on the design and optimization of current mirror MOSFET embedded pressure sensor. A current mirror circuit with an output current of 1 mA integrated with a pressure sensing n-channel MOSFET has been designed using standard 5 µm CMOS technology. The channel region of the pressure sensing MOSFET forms the flexible diaphragm as well as the strain sensing element. The piezoresistive effect in MOSFET has been exploited for the calculation of strain induced carrier mobility variation. The output transistor of the current mirror forms the active pressure sensing MOSFET which produces a change in its drain current as a result of altered channel mobility under externally applied pressure. COMSOL Multiphysics is utilized for the simulation of pressure sensing structure and Tspice is employed to evaluate the characteristics of the current mirror pressure sensing circuit. Simulation results show that the pressure sensor has a sensitivity of 10.01 mV/MPa. The sensing structure has been optimized through simulation for enhancing the sensor sensitivity to 276.65 mV/MPa. These CMOS-MEMS based pressure sensors integrated with signal processing circuitry on the same chip can be used for healthcare and biomedical applications.

Current Mirror Circuits with Improved Performance

Current mirrors are core structures for almost all analog mode circuits and are integral part of a signal processing elements like op amps. The performance of analog structures largely depends on their characteristics. In this paper we present some of the current mirror circuits and analyze their performances, so that one can choose a suitable current mirror for a particular application.

Physics-Based SPICE Model of Spin-Torque Oscillators

The spin-torque oscillator (STO) is a new compact device operating as a tunable RF oscillator in the tens of gigahertz range whose characteristics are determined by the applied current and magnetic field. In this paper, we present a physics-based empirical circuit-level model of an STO that is compatible with circuit-level simulators such as SPICE. The characteristics of an STO are modeled as physics-based analytic functions of the applied current and external magnetic field. The validity of our model was verified by the HSPICE simulation of a current mirror circuit that contains an STO element. The simulation results are in good agreement with the experimental data in the normal operation range. High-order nonlinear effects at large currents are not included in our model because there is no theoretical equation available yet that can precisely explain these effects.