Current Mirror Circuit Research Articles

A numerical analysis of a CMOS image sensor with a simple fixed-pattern-noise-reduction technology

A 1/3-in 640/spl times/480-pixel CMOS image sensor with a simple fixed-pattern noise-reduction technology with a five-transistor pixel circuit and a low input-voltage current-voltage (I-V) converter was previously developed. In this report, we show that the low-input-voltage I-V converter with a current-mirror circuit improves the amplification factor and linearity of the pixel circuit. In a five-transistor pixel circuit, the threshold voltage of the X-Y addressing transistor affects the amplitude and the level of the readout pulse. An analysis of the mechanism of the X-Y addressing transistor shows the basic concept behind the selection of the threshold voltage. An L-shaped readout gate for a pinned photodiode is compared with a straight readout gate, and is proved to be adequate for rapid charge transfer.

Realization of a multiport gyrator using current mirror circuits

AbstractA current‐mode signal processing circuit is quite attractive for low supply voltage operation and high‐frequency application. A current‐mode continuous‐time filter consists of simple bipolar current mirrors and capacitors, and are quite suitable for monolithic integration. In this paper, we propose a design for a multiport gyrator using current mirror circuits. Using the multiport gyrator and capacitors, we can simulate passive LC filters. The tuning of the filter frequency can be achieved by adjusting the current of a single dc current course. As examples, third‐ and fifth‐order low‐pass filters are designed for frequencies of 20 to 80 MHz, and SPICE simulation results are shown to demonstrate the effectiveness of the proposed method. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 139(4): 41–47, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.1167

簡素で効果的な固定パターンノイズ抑圧を実現したＣＭＯＳイメージセンサの動作解析

A 1/3-inch 640×480-pixel CMOS image sensor was developed using a simple fixed-pattern-noise-reduction technology with a five-transistor pixel circuit and a low input-voltage I-V converter. In this report, we show the effectiveness of a low input-voltage I-V converter with a current-mirror circuit in improving the amplification ratio and linearity of a pixel circuit. The dependence of the pixel signal characteristics on the parameters of the pixel transistors was also analyzed. In a five-transistor pixel circuit, the threshold voltage of the X-Y addressing transistor affects the amplitude and level of the readout pulse. This report also contains analysis of the mechanism of the X-Y addressing transistor, illustrating the concept behind the selection of the threshold voltage.

Switched-current bilinear integratorrealised using one current-mirror

A family of new bilinear switched-current integrator circuits is presented. The main advantage of the proposed circuits is that the effect of transistor mismatches is minimised. This is achieved using a new z-domain block diagram that can be implemented using a reduced number of current-mirror circuits. Comparison shows that the proposed circuits have favourable characteristics.

Exploiting electrothermal oscillations for identifying MOSFET thermal parameters

Electrothermal oscillations in electronic circuits are in general regarded as parasitic dynamic phenomena. This paper shows how these phenomena may be exploited to identify the value of thermal resistance and capacitance of the RC network modelling heat diffusion. Measurement of the period of oscillations and bifurcation analysis of the stability of the equilibrium point are two approaches that may possibly lead to a reasonable estimate of these parameters. In this paper, we present both methods applied to two specific MOSFET circuits. In particular, the oscillation period of a current-mirror circuit and bifurcation analysis of a simple one-MOSFET circuit are analysed in detail. For the bifurcation analysis approach, theory and experimental results are successfully compared to simulation in order to validate the proposed model.

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20 MS/s and 54-dB S/N at 30 MS/s

A new video-speed current-mode CMOS sample-and-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feed through, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6-/spl mu/m MOS devices with normal threshold voltages (V/sub th/) of +0.7 V (nMOS) and -0.7 V (pMOS).

カレントミラー回路を用いた多端子対ジャイレータの実現

カレントミラー回路を用いた多端子対ジャイレータの実現

A high-precision low-voltage bipolar current mirror circuit and its compensation for stability

A current mirror circuit is widely utilized as an important building block in analogue signal processing circuits. This paper describes a high-precision low voltage bipolar current mirror circuit. Well known current mirror circuits, such as a simple current mirror and a Wilson current mirror, have a trade-off between low-voltage operation and accuracy of the current gain. The accuracy of the proposed current mirror is high in spite of low current amplification factor (β) of transistors and large current output (or a large number of the multiple output). The current mirror circuit can operate at a 1V or less supply voltage. The high accuracy is realized by negative current feedback with high gain. Thus, the stability of the circuit and compensation methods are discussed. PSPICE simulation shows that the proposed current mirror circuit compensated using Miller components composed of a capacitor and a resistor is stable and can operate at a 1V supply voltage.

ニューロンMOSカレントミラー回路

This paper presents a design of a neuron-MOSFET current mirror circuit. This current mirror is built with neuron-MOSFETs and a differential amplifier. The influence of the channel-length-modulation and initial charge of floating gate are minimized by adopting feedback of differential signal. The performance of the proposed circuit is predicted by theoretical analysis and PSPICE simulation.

A Low-Loss Built-In Current Sensor

This paper presents a novel built-in current sensor that uses two additional power supply voltages besides the system power supply voltage, and that is constructed by using a current mirror circuit...

Switched-current integrator with reduced transient glitches

An improved SI integrator circuit with reduced amplitude of transient glitches is proposed. The main advantage of the proposed topology is that, using an extra current mirror circuit, the same reduction of transient glitches is achieved as in the case in which an op-amp configuration was used.

5526215 Secondary cell protection unit for protecting a secondary cell from overdischarge or overcharge without excessive power consumption

A secondary battery protection unit comprises a discharge switch (41) and a charge switch (42) inserted in an electric path between a positive terminal (B1) and a negative terminal (B2) together with secondary cells (1 and 2) connected in cascade to the discharge and the charge switches (41 and 42), overcharge detection circuits (45 and 46), and an activation control circuit (17) including a current mirror circuit. The activation control circuit (17) detects a voltage difference between both ends of a combination or one of the discharge and the charge switches (41 and 42) to judge whether or not the secondary cells perform a charging operation or a discharging operation. Only during the charging operation, the activation control circuit (17) makes the current mirror circuit supply a bias voltage to the overcharge detection circuits (45 and 46) to allow activation thereof. During the discharging operation, supply of the bias voltage is inhibited to save excessive power consumption.

An AlGaAs/InGaAs pseudomorphic HEMT modulator driver IC with low power dissipation for 10-Gb/s optical transmission systems

An optical modulator driver integrated circuit (IC) has been developed for 10-Gb/s optical communication systems. To achieve both high-frequency (HF) operation and low power dissipation, 0.2-/spl mu/m T-shaped gate AlGaAs/InGaAs pseudomorphic high electron-mobility transistors (HEMTs) have been employed for their large transconductance g/sub m/ of 610 mS/mm and high cutoff frequency f/sub T/ of 67.5 GHz. In addition, optimizing input logic swing, switching transistor size in the output driver, and using cascode-current mirror circuits with small output conductance enable power dissipation as low as 1 W to be achieved at a 10-Gb/s nonreturn-to-zero (NRZ) signal output with 3 V/sub p/./sub p/. This is the lowest value ever reported for power dissipation. As an additional function, the output-voltage swing can be controlled in the range from 2 to 3.3 V/sub p/./sub p/. by the current mirror circuit for the purpose of adjusting the optical-output-signal duty factor through an optical modulator.

A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF).

A realization of a high-frequency monolithic integrator with low power dissipation and its application to an active RC filter

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great difficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.

Optimizing the match in weakly inverted MOSFET's by gated lateral bipolar action

The on-chip n-type MOSFET current mirror circuit with different drawn gate widths and lengths has been fabricated, and has been characterized across the wafer with back gate slightly forward biased. The weakly inverted MOSFET device with a small back-gate forward bias represents equivalently the high-gain gated lateral bipolar transistor in low-level injection. Experimental results have exhibited a substantial improvement in the match of the drain current in weak inversion due to action of the gated lateral bipolar transistor, especially for the small size devices. The extensively measured mismatch of the weak inversion drain current has been successfully reproduced by an analytic statistical model with back-gate forward bias and device size both as input parameters. The experimentally extracted variations in process parameters such as the flat-band voltage and the body effect coefficient each have been found to follow the inverse square root of the device area. The mismatch model thus can serve as a quantitative design tool, and has been used to optimize the trade-off between the device area and the match with the forward back-gate bias as a parameter.

A monolithic DC temperature compensation bias scheme for multistage HEMT integrated circuits

This work benchmarks the first demonstration of a multistage monolithic HEMT IC design which incorporates a DC temperature compensated current-mirror bias scheme. This is believed to be the first demonstrated monolithic HEMT bias scheme of its kind. The active bias approach has been applied to a 2-18 GHz five-section low noise HEMT distributed amplifier which achieves a nominal gain of 12.5 dB and a noise figure <2.5 dB across a 2-18 GHz band, The regulated current-mirror scheme achieves better than 0.2% current regulation over a 0-125/spl deg/C temperature range, The RF gain response was also measured over the same temperature range and showed less than 0.75 dB gain degradation. This results in a -0.006 dB//spl deg/C temperature coefficient which is strictly due to HEMT device G/sub m/ variation with temperature. The regulated current-mirror circuit can be employed as a stand-alone V/sub gs/-voltage reference circuit which fan be monolithically applied to the gate bias terminal of existing HEMT ICs for providing temperature compensated performance, This monolithic bias approach provides a practical solution to DC bias regulation and temperature compensation for HEMT MMICs which can improve the performance, reliability, and cost of integrated microwave assemblies (IMAs) used in space-flight military applications.

Thermal and reverse base current effects on heterojunction bipolar transistors and circuits

An empirical model of a heterojunction bipolar transistor is presented. The model expands the Gummel-Poon equations to account for device self-heating, base current reversal, and the collector-emitter offset voltage. It is shown that self-heating has implications for the cutoff frequency of the HBT, for the frequency response of a small-signal amplifier, and also for the thermal stability of a current mirror circuit.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed current mirror resistive compensationtechnique

In the Letter the authors propose a very simple but powerful method of speed and bandwidth enhancement for general CMOS current mirror circuits. Introducing a compensation resistor between the gates of the primary transistor pair of the current mirror can lead to a significant bandwidth enhancement. Simulated and measured results are presented.

The active-input regulated-cascode current mirror

A continuous-time current mirror circuit is presented that combines an active input and a regulated cascode output. The current mirror offers a high accuracy over an operating current range higher than previous structures. Results are demonstrated through Hspice nominal and Monte Carlo simulations. >