Conventional Domino Research Articles

An efficient common source sense amplifier for single ended SRAM

Sense amplifiers (SA) play a vital role in supporting the read performance of static random-access memory (SRAM). Single ended SRAM has attracted importance due to low leakage current and absence of time margin compared to differential SA. This paper proposes a common source sense amplifier (CSSA) for low power single ended SRAM for read operation. The sense amplifier performs dual task by charging the bit line during pre-charge phase and amplifying the bit line during evaluation phase. The proposed CSSA shows good improvement in sensing time and power at higher number of cells per bit line (CpBL). The proposed CSSA exhibits 53%, 48%, 24%, 23%, and 41% lower sensing time for 256 CpBL and 52%, 51%, 50%, 37%, and 47% lesser power consumption than the conventional domino sensing scheme (DSS), AC coupled sense amplifier (ACSA), non-strobed regenerative sense amplifier (NSRSA), switching PMOS sense amplifier (SPSA) and trip point bit line pre-charge sensing scheme (TBPSS). The proposed CSSA occupies 18%, 25%, 53%, 61%, and 37% lesser area compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA has 88%, 88%, 85%, 91%, and 87% lesser APDP (area power delay product) compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA sensing scheme is implemented and simulated in Cadence Virtuoso tool with 45 nm technology. The simulation results of CSSA prove that the proposed CSSA sense amplifier is suitable for high speed and low power SRAM architecture.

Proposed time‐mode wide fan‐in NAND and NOR gates

SummaryCMOS circuits usually operate either in the voltage, current, charge, or time domain. Each of these domains has its own features. As the fan‐in of CMOS circuits increases, the performance of circuits that operate in the voltage domain, the current domain, or the charge domain degrades. This is the case especially with scaling down the power‐supply voltage associated with technology scaling. In this paper, a time‐mode scheme that utilizes a floating‐gate MOSFET (FGMOS) transistor is proposed. The proposed scheme showed good performance for wide fan‐in NAND and NOR gates. The design issues of the proposed scheme like the speed and the power consumption are investigated quantitatively. The performance of the proposed scheme is confirmed through simulation using the 45‐nm CMOS predictive technology model (PTM) with a 1‐V power‐supply voltage. 64‐input NAND and NOR gates realized using this scheme have time delays of 0.375 and 0.25 ns, respectively, at a load capacitance of 5 fF. The application of the proposed scheme for realizing multiplexers required in register files is illustrated and compared with the conventional domino logic in the superthreshold, near‐threshold, and subthreshold regions.

A Novel Domino Logic Based on Floating-Gate MOS Transistors

Domino logic finds a wide variety of applications in both static and dynamic random-access memories and in high-speed microprocessors. However, the main limitation of the domino logic-circuit family is the trade-off between the noise immunity and speed. In order to resolve such a trade-off, this paper proposes a domino logic that is based on floating-gate MOS (FGMOS) transistors. Compact-form expressions are derived for the noise margins for the low and high inputs as well as the propagation delays. The proposed scheme is verified by simulation adopting the 45 nm CMOS predictive technology model (PTM) with a power-supply voltage of 1 V. The obtained results unveil that the proposed domino logic outperforms the conventional domino logic in terms of the power-delay product and the energy-delay product when realizing wide fan-in OR gates. The realized, with the proposed scheme, 16-input OR gate has an average power consumption of 3.7 µW and a propagation delay of 51 ps.

Reduction of variation and leakage in wide fan-in OR Logic domino gate

In this paper, a novel domino gate is proposed to decrease the process variability and leakage current with enhanced noise margin for wide fan-in OR logic. The process variation is decreased by reducing the transconductance of the keeper transistor, whereas the subthreshold leakage current is decreased by redesigning the evaluation network. In addition, a keeper-controlled network is developed to control the switching activity of keeper which eventually reduces the power dissipation. Further, extensive analysis of reliability is accomplished against the process, voltage, and temperature. Further, 64-word*32bit Read ported register file is designed to show the supremacy of proposed domino gate over the conventional domino. All proposed circuits are designed, simulated and verified using SPECTRE simulator in CADENCE VIRTUOSO at 45 nm CMOS technology node. The results reveal that power and delay variability are reduced by 55% and 57%, whereas noise margin is improved by 74% with respect to reported conventional domino. Hence, the analysis suggests that proposed domino circuit can be useful to implement deep submicron low power VLSI circuits.

A Low-Power High-Speed Sensing Scheme for Single-Ended SRAM

In this paper, a reference-voltage self-selected pseudo-differential sensing scheme suitable for single-ended SRAM is proposed. The proposed sensing scheme can select different reference voltage according to the offset direction. With the employment of the new sensing scheme, the swing of the read bit-line in the read operation is reduced by 74.6% and 45.5% compared to the conventional domino and the pseudo-differential sense amplifier sensing scheme, respectively. Therefore, the delay and power consumption of the read operation are significantly improved. Simulation results based on a standard 55nm CMOS show that compared with the conventional domino and pseudo-differential sensing schemes, the sensing delay is improved by 66.4% and 47.7%, and the power consumption is improved by 31.4% and 22.5%, respectively. Although the area of the sensing scheme is increased by 50.8% compared with the pseudo-differential sense amplifier sensing scheme, it has little effect on the entire SRAM area.

Harnessing Cascading Dominoes for Peristaltic Wave Motion

Organisms have evolved many simple yet effective muscular movements. Of these, peristaltic wave motion is among the most prolific and can be found across organism scales and in a variety of organs that transport objects or provide locomotion. Several robotic platforms have mimicked peristaltic movement, which resembles soliton propagation; however, the complexity of integrating multiple sequential actuators and the fragility of these systems have limited their practical application. In this work, we demonstrate the potential of cascading dominoes to realize soliton-like wave movements that can transport objects and locomote with only two actuators. Unlike conventional domino series where falling dominoes produce a soliton at the collapsing frontier, we added a revolute joint on each domino to ensure all the dominoes stack continuously, which inherently changes the soliton wave shape. We show how domino geometry determines the wave shape of the soliton, both analytically and experimentally, and how actuator speed affects the wave speed. Inspired by peristaltic wave motion in living organisms, we used the cascading dominoes to move objects through an artificial esophageal conduit and build a “mantis shrimp” crawler. Cascading dominoes enable a new type of actuator mechanism and provide new opportunities for robotic motion.

A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-In OR Logic

This paper proposes a novel method to control leakage and noise in domino circuits for wide fan-in OR logic with low power consumption, low process variation, and higher noise margin under the similar delay condition. In the proposed method, output and dynamic nodes are isolated from the PDN (Pull-Down Network) to improve the noise immunity and reduce switching activity. Further, with the aid of a transistor in the stack, the sub-threshold current is reduced. Thus, the proposed domino is applicable for high-speed and low-power applications in deep sub-micro-range. Simulation results show that the proposed domino improves the noise immunity and figure of merit (FOM) by factors of 1.95 and 2.34, respectively, with respect to the conventional domino with a footer. Along with this improvement, 26% reduction is also observed in power consumption. The entire simulations for all the domino circuits are done at 45-nm CMOS technology by using SPECTRE simulator under the Cadence Virtuoso environment.

Design of Arithmetic Logic Unit using Pseudo Dynamic Buffer based Domino Logic

Design of combinational circuits using dynamic logic has the advantage of high speed and less area when compared to conventional CMOS logic. However, it pose problem while cascading dynamic logic architectures and also more prone to leakage current issue. These issues are overcome by using domino logic with static inverter at the output of dynamic node. The increased power dissipation at the output node is reduced by using pseudo dynamic buffer based domino logic by having static like switching at the output node. This paper details the design of arithmetic and logic unit designed using conventional and pseudo dynamic buffer based domino logic. The arithmetic unit comprise adder, subtractor, multiplier and logical unit comprise AND, NAND, OR, NOR and XOR logic blocks based on pseudo dynamic buffer based domino logic and it is compared with the Arithmetic logic unit designed using conventional domino logic. The design and simulations are performed using UMC90nm technology node library using Cadence® Virtuoso® tool. The simulation result of ALU unit demonstrates that arithmetic logic unit designed using PDB logic has reduction in power consumption by 89.14% and delay by 1.995% while compared to conventional domino logic.

A Novel Low Power Technique for FinFET Domino OR Logic

Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the main reason of large power dissipation in electronic circuits. Very large-scale integration (VLSI) industry has chosen an alternative option known as fin-shaped field effect transistor (FinFET) technology to mitigate the large power dissipation. FinFET is a multi-gate transistor which dissipates less leakage power as compared to CMOS transistors, but it does not completely resolve the problem of power dissipation. So, leakage reduction approaches are always required to mitigate the impact of power dissipation. In this paper, cascaded leakage control transistors (CLCT) leakage reduction technique is proposed using FinFET transistors. CLCT approach is tested for basic static logic circuits like inverter, 2-input NAND and NOR gates and compared with the existing leakage reduction techniques for leakage power dissipation and delay calculations at 16 and 14 nm technology nodes using Cadence tools. CLCT approach shows the effective reduction of leakage power with minimum delay penalty. As the domino logic gates are widely used in large memories and high-speed processors therefore, CLCT approach is further utilized for footless domino logic (FLDL) and compared with the available methods at 14[Formula: see text]nm technology node. CLCT approach reduces 35.16% power dissipation as compared to the conventional domino OR logic. Temperature and multiple parallel fin variations are estimated for the domino OR logic to check its reliable operation. CLCT approach has high-noise tolerance capability in term of unity noise gain (UNG) for domino OR logic as compared to the other methods.

Speed enhancement techniques for Clock-Delayed Dual Keeper Domino logic style

ABSTRACT Domino circuit topology for high-speed operation, robustness and lower power consumption is quintessential in design of digital systems. In this paper, various high speed and robust mechanisms are proposed to enhance the speed of Clock-Delayed Dual Keeper Domino (CDDK) circuit. Delayed enabling of keeper circuit in CDDK domino circuit reduces contention between keeper circuit and Pull-Down network (PDN). The speed of transition at the dynamic node of the CDDK domino circuit is enhanced through imposing techniques namely (i) controlled clock delay time in enabling the keeper transistor, (ii) keeper control signal voltage swing variation, (iii) sizing of keeper transistors and (iv) deploying an additional conditional discharge path. The robustness of CDDK circuit is increased by upsizing the keeper transistor without degrading the speed by stack arrangement of dual keeper transistors. The simulation of enhancement techniques has been performed using Cadence® Virtuoso ADEL and ADEXL environments employing UMC 90nm technology library. The simulation results of wide fan-in 64-input OR gate demonstrate that CDDK technique with additional discharge path offer 38% increase in speed and CDDK technique with keeper transistor upsizing offers 52% increase in noise gain margin without speed degradation while comparing with the conventional domino logic circuit.

Clock Delayed Dual Keeper Domino Logic Design with Reduced Switching

Clock Delayed Dual Keeper domino logic style with Static Switching mechanism (CDDK_SS) using delayed enabling of the keeper circuit and modified discharge path has been proposed in this paper. In CDDK domino circuit, the principle of delayed enabling of keeper circuit offers reduced contention between keeper circuit and Pull Down Network (PDN). The modified discharge path at the output node eradicates the switching at the output node for identical TRUE inputs during the pre-charge phase. This facilitates in obtaining static like output in contrast with conventional domino logic. The simulation results of Arithmetic and Logic Unit (ALU) subsystems demonstrate 17.7% reduction in dynamic power consumption while compared to conventional domino logic. Furthermore, 62% enhancement in speed performance has been achieved with good robustness. Design and simulation have been executed using Cadence® Virtuoso, with UMC 90nm technology node library.

Design impacts of delay invariant high‐speed clock delayed dual keeper domino circuit

Precise keeper control of domino logic circuit can significantly increase the speed of operation. However, the positive feedback gain associated with the feedback keeper circuit unduly increases the delay variability. Here, a novel high-speed clock delayed dual keeper (CDDK) domino circuit is presented, which aims at reducing the delay and lower the impact of loop gain on delay variability. In CDDK domino structure, the keeper circuit comprising of two keeper devices is disabled during the initial evaluation phase. This significantly reduces the contention current and thereby the operating speed of the circuit is enhanced. The simulations of the circuits have been carried out for various metrics and the results have been analysed. Furthermore, the Monte-Carlo simulations carried out for 2000 runs on a 128-input OR gate using CDDK structure demonstrate reduced delay variability characteristics due to smaller loop gain of the CDDK domino structure against the conventional domino logic style. The enhanced speed of operation due to reduced contention current is demonstrated. The results are validated through comparison against the conventional domino logic counterpart circuits. The analyses of the circuits are performed using industry standard full-suite Cadence® tools using 90 nm technology library.

Modified Keeper Controlled Domino Circuit for Low Power High Performance Wide Fan in OR Gates

A novel modified keeper technique has been proposed in this paper for domino logic circuits implemented as wide fan in OR gate. Few circuit parameters as capacitivie loading and delay are major concerns for OR gates in deeper technology nodes. This design focuses on a comparator block with modified dual keeperto maintain the output logic state. Additionally it comprises of a delay loop to limit the contention current. The proposed design reduces the input capacitive loading and total power consumption by the circuit, while keeping the speed of operation same. It was compared with latest domino circuit techniques and the proposed design MKCD has achieved a reduction of 41% in power consumption in 64 bit configuration as compared to conventional domino circuit SFLD. Average noise immunity has also increased by more than twice as compared to SFLD. The simulations were performed using 90nm PTM low power models.

A new process variation and leakage-tolerant domino circuit for wide fan-in OR gates

In this work, a new technique for domino circuit is proposed to reduce the process variations and power dissipation with optimized delay for wide fan-in OR logic. Two methods are used to reduce both process variation and power dissipation at the same time. In first part, the keeper circuit has been redesigned to reduce the process variation with enhanced noise margin. And in second part, evaluation network has been redesigned to reduce the subthreshold leakage current at optimized delay. Thus, the proposed domino can be used to design the low power VLSI circuits and deep submicron regime. The simulation results show that this work exhibits about 64% and 30% process variations reduction in power, and 38% and 21% process variations reduction in delay for reported conventional domino and a simple approach for delay reduction domino respectively. Noise margin is also improved by 1.41 and 1.16 times compared to above said schemes respectively. All simulation results are obtained with Cadence Virtuoso environment using SPECTRE simulator for 45 nm CMOS technology.

Ultralow power, noise immune stacked‐double stage clocked‐inverter domino technique for ultradeep submicron technology

SummaryHigh‐performance system widely uses domino gates due to their high speed and low power. Everlasting demand of technology scaling increases leakage current in domino gates. These make domino circuit less immune to noise. This paper present a new energy efficient circuit technique for ultralow power consumption and higher noise immunity design for wide fan‐in gates. The proposed circuit techniques reduce leakage from the evaluation network of the domino circuit with help of stacked footer approach involving clocked inverter in double stage domino. This approach has an added advantage of circuit robustness. The proposed circuit exerts less power dissipation and improved unity noise gain compared with a conventional domino circuit. The immunity is demonstrated with the help of average noise threshold energy, energy normalized ANTE (ANTE, ANTE/Energy). The simulation of the circuit is carried out by using 90 nm technology in Cadence TCAD tools.

Contention free delayed keeper for high density large signal sensing memory compiler

Compiler based embedded memory is essential for SoC design. A new Contention Free Delayed Keeper (CFDK) topology has been developed in a leading edge 14 nm System-on-Chip (SoC) technology to improve the read performance of register file (RF) memories which can be easily used for both high density (HD) and high performance (HP) RF memory compiler design. This technique never allows contention and this helps to improve Vmin (minimum operating voltage at which design is functional) significantly compared to a conventional keeper with low area overhead. It does not require fine tuning the keeper delay across the range of the local bit line (LBL) lengths that the compiler supports. It is shown that the proposed technique enhances the circuit evaluation speed by at least 68% while reducing power dissipation by 2.75% as compared to conventional domino logic. It also shows minimum 10% improvement in area with at par or better Vmin and performance over other delayed keeper techniques. The same technique can be broadly applied to any domino path design including ROM design.

A new low-power dynamic circuit for wide fan-in gates

In this paper, a new dynamic circuit is proposed to reduce the power consumption of wide fan-in gates. Since the voltage difference across the pull-down network determines the output in the proposed circuit, the voltage swing on the pull-down network can be lowered to decrease the dramatically increasing power consumption of wide fan-in gates. Wide fan-in OR gates are designed and simulated using the proposed domino circuit in 90nm CMOS technology. Simulation results exhibit up to 2.62X improvement in noise immunity and 44% reduction in power consumption compared to the conventional domino circuits at the same delay. Moreover, a 2-read, 1-write ported 64-word × 32-bit/word register file is designed using the proposed domino circuit. The Register file is simulated using low-Vth 90nm CMOS model in all process corners. The results shows 25% power reduction and 32% speed improvement for the proposed register file in comparison with the conventional register file at the same noise margin floor.

Controlled delay‐through dynamic logic: leakage‐tolerant high‐speed dynamic logic

A new model for dynamic logic is proposed with low power consumption and leakage without the degradation of speed. This logic works perfectly with cascaded and differential style without inverters. Controlled delay-through dynamic logic (CDTDL) is comparatively faster than other dynamic logics because of the parallel-type configuration with clock and inputs. CDTDL-based circuits can perform better in high-frequency operations due to lower propagation delay and dynamic power consumption at the cost of area. The proposed technique can avoid the chance of leakage current with the help of a control block and a delayed clock mechanism. The simulation results show that the new dynamic logic using 180 nm technology yields a minimum 49.7% improvement in power delay product compared with its predecessors such as conventional domino and current comparison-based domino for standard circuits.

Small‐swing domino logic based on twist‐connected transistors

A new small-swing domino logic that reduces the signal amplitude by adding twist-connected PMOS and NMOS transistors in the conventional domino logic is presented. The circuit lowers the voltage level of a logic `1' and increases the voltage level of a logic `0' while maintaining the logic threshold at half of the supply voltage. The output swing range of the proposed circuit can be modulated by varying the size of the twist-connected transistors and the load capacitance. The 32-bit ripple carry adders designed with the proposed circuit technique reduce power consumption by 37% and the power-delay product (PDP) performance by 43%, as compared with the power consumption and PDP performance of the domino CMOS logic. Thus, the proposed circuit effectively reduces power consumption with the use of the new small-swing domino logic.

Low power wide gates for modern power efficient processors

In this paper, a low power register file and tag comparator is proposed which has lower leakage and higher noise immunity without dramatic speed degradation due to the wide fan-in gates. Simulation of register files and tag comparators designed is done using low-Vth 90nm CMOS process technology model in all process corners. The results demonstrate 20% power reduction and 2× noise-immunity improvement in the implemented register file using the proposed circuit at the same delay compared to the standard domino circuits. On the other hand, simulation of tag comparators implemented using the other proposed circuit shows 41%, 22% and 7.5% reduction in power, delay and area, respectively compared to the standard footless domino at the same robustness condition. Moreover, the register file and the tag comparator designed with the proposed circuits respectively show 2.48 and 3 times improvement in the defined figure of merit compared to the counterpart circuits designed with the conventional domino circuit. Thus, the proposed are power efficient and suitable approaches for embedded processors with multi-ported register file and fully-associative caches with large number of tag comparators.